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Antonia Zhai
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2020 – today
- 2024
- [c38]Kartik Ramkrishnan
, Stephen McCamant
Non-Fusion Based Coherent Cache Randomization Using Cross-Domain Accesses. AsiaCCS 2024 - [c37]Ziyan Wu, Yang Zhang, Feng Tian, Minjun Wu, Antonia Zhai, Zhi-Li Zhang:
Interleaved Function Stream Execution Model for Cache-Aware High-Speed Stateful Packet Processing. ICDCS 2024: 531-542 - 2022
- [j13]Ziyan Wu, Tianming Cui, Arvind Narayanan, Yang Zhang, Kangjie Lu, Antonia Zhai, Zhi-Li Zhang:
GranularNF: Granular Decomposition of Stateful NFV at 100 Gbps Line Speed and Beyond. SIGMETRICS Perform. Evaluation Rev. 50(2): 46-51 (2022) - [c36]Minjun Wu, Stephen McCamant, Pen-Chung Yew
PREDATOR: A Cache Side-Channel Attack Detector Based on Precise Event Monitoring. SEED 2022: 25-36 - 2020
- [c35]Wenwen Wang, Pen-Chung Yew
Efficient and scalable cross-ISA virtualization of hardware transactional memory. CGO 2020: 107-120 - [c34]Kartik Ramkrishnan, Stephen McCamant, Pen-Chung Yew
First Time Miss : Low Overhead Mitigation for Shared Memory Cache Side Channels. ICPP 2020: 36:1-36:11 - [c33]Jieming Yin, Antonia Zhai:
In-Network Memory Access Ordering for Heterogeneous Multicore Systems. NOCS 2020: 1-8
2010 – 2019
- 2019
- [c32]Changheng Song, Wenwen Wang, Pen-Chung Yew, Antonia Zhai, Weihua Zhang:
Unleashing the Power of Learning: An Enhanced Learning-Based Approach for Dynamic Binary Translation. USENIX ATC 2019: 77-90 - [i1]Kartik Ramkrishnan, Antonia Zhai, Stephen McCamant, Pen-Chung Yew:
New Attacks and Defenses for Randomized Caches. CoRR abs/1909.12302 (2019) - 2018
- [c31]Wenwen Wang, Stephen McCamant, Antonia Zhai, Pen-Chung Yew
Enhancing Cross-ISA DBT Through Automatically Learned Translation Rules. ASPLOS 2018: 84-97 - 2017
- [c30]Wenwen Wang, Pen-Chung Yew
Enabling Cross-ISA Offloading for COTS Binaries. MobiSys 2017: 319-331 - 2016
- [c29]Wenwen Wang, Pen-Chung Yew, Antonia Zhai, Stephen McCamant:
A General Persistent Code Caching Framework for Dynamic Binary Translation (DBT). USENIX ATC 2016: 591-603 - 2015
- [j12]Anup Holey, Vineeth Mekkat, Pen-Chung Yew
Performance-Energy Considerations for Shared Cache Management in a Heterogeneous Multicore Processor. ACM Trans. Archit. Code Optim. 12(1): 3:1-3:29 (2015) - [j11]Ragavendra Natarajan, Antonia Zhai:
Leveraging Transactional Execution for Memory Consistency Model Emulation. ACM Trans. Archit. Code Optim. 12(3): 29:1-29:24 (2015) - [j10]Michael Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy L. Allmon, Neal Clayton Crago, Kermin Fleming, Mohit Gambhir, Aamer Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, Joel S. Emer:
Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures. ACM Trans. Comput. Syst. 33(3): 10:1-10:32 (2015) - 2014
- [j9]Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer:
Efficient Spatial Processing Element Control via Triggered Instructions. IEEE Micro 34(3): 120-137 (2014) - [j8]Zhenman Fang, Sanyam Mehta, Pen-Chung Yew
Measuring Microarchitectural Details of Multi- and Many-Core Memory Systems through Microbenchmarking. ACM Trans. Archit. Code Optim. 11(4): 55:1-55:26 (2014) - [c28]Anup Holey, Antonia Zhai:
Lightweight Software Transactions on GPUs. ICPP 2014: 461-470 - [c27]Sanyam Mehta, Zhenman Fang, Antonia Zhai, Pen-Chung Yew
Multi-stage coordinated prefetching for present-day processors. ICS 2014: 73-82 - [c26]Jieming Yin, Pingqiang Zhou, Sachin S. Sapatnekar
Energy-Efficient Time-Division Multiplexed Hybrid-Switched NoC for Heterogeneous Multicore Systems. IPDPS 2014: 293-303 - 2013
- [j7]Yangchun Luo, Wei-Chung Hsu
The design and implementation of heterogeneous multicore systems for energy-efficient speculative thread execution. ACM Trans. Archit. Code Optim. 10(4): 26:1-26:29 (2013) - [c25]Vineeth Mekkat, Anup Holey, Pen-Chung Yew
Managing shared last-level cache in a heterogeneous multicore processor. PACT 2013: 225-234 - [c24]Anup Holey, Vineeth Mekkat, Antonia Zhai:
HAccRG: Hardware-Accelerated Data Race Detection in GPUs. ICPP 2013: 60-69 - [c23]Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer:
Triggered instructions: a control paradigm for spatially-programmed architectures. ISCA 2013: 142-153 - [c22]Vineeth Mekkat, Anup Holey, Antonia Zhai:
Accelerating Data Race Detection Utilizing On-Chip Data-Parallel Cores. RV 2013: 201-218 - 2012
- [j6]Ragavendra Natarajan, Vineeth Mekkat, Wei-Chung Hsu
Effectiveness of Compiler-Directed Prefetching on Data Mining Benchmarks. J. Circuits Syst. Comput. 21(2) (2012) - [j5]Shengyue Wang, Pen-Chung Yew
Code Transformations for Enhancing the Performance of speculatively Parallel Threads. J. Circuits Syst. Comput. 21(2) (2012) - [j4]Yangchun Luo, Antonia Zhai:
Dynamically dispatching speculative threads to improve sequential execution. ACM Trans. Archit. Code Optim. 9(3): 13:1-13:31 (2012) - [c21]Jieming Yin, Pingqiang Zhou, Anup Holey, Sachin S. Sapatnekar
Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems. ISLPED 2012: 57-62 - 2011
- [j3]Guojin He, Antonia Zhai:
Efficient dynamic program monitoring on multi-core systems. J. Syst. Archit. 57(1): 121-133 (2011) - [c20]T. Kolpe, Antonia Zhai, Sachin S. Sapatnekar:
Enabling improved power management in multicore processors through clustered DVFS. DATE 2011: 293-298 - [c19]Pingqiang Zhou, Jieming Yin, Antonia Zhai, Sachin S. Sapatnekar:
NoC frequency scaling with flexible-pipeline routers. ISLPED 2011: 403-408 - 2010
- [c18]Yangchun Luo, Venkatesan Packirisamy, Wei-Chung Hsu
Energy efficient speculative threads: dynamic thread allocation in Same-ISA heterogeneous multicore systems. PACT 2010: 453-464 - [c17]Guojin He, Antonia Zhai:
Improving the performance of program monitors with compiler support in multi-core environment. IPDPS 2010: 1-12
2000 – 2009
- 2009
- [c16]Venkatesan Packirisamy, Antonia Zhai:
Exploiting TLS Parallelism at Multiple Loop-Nest Levels. ICPADS 2009: 205-212 - [c15]Yangchun Luo, Venkatesan Packirisamy, Wei-Chung Hsu
Dynamic performance tuning for speculative threads. ISCA 2009: 462-473 - [c14]Venkatesan Packirisamy, Antonia Zhai, Wei-Chung Hsu
Exploring speculative parallelism in SPEC2006. ISPASS 2009: 77-88 - [c13]Antonia Zhai, Guojin He, Mats Per Erik Heimdahl:
Hardware Supported Flexible Monitoring: Early Results. RV 2009: 168-183 - 2008
- [j2]Antonia Zhai, J. Gregory Steffan, Christopher B. Colohan, Todd C. Mowry:
Compiler and hardware support for reducing the synchronization of speculative threads. ACM Trans. Archit. Code Optim. 5(1): 3:1-3:33 (2008) - [c12]Venkatesan Packirisamy, Yangchun Luo, Wei-Lung Hung, Antonia Zhai, Pen-Chung Yew
Efficiency of thread-level speculation in SMT and CMP architectures - performance, power and thermal perspective. ICCD 2008: 286-293 - [c11]Antonia Zhai, Shengyue Wang, Pen-Chung Yew
Compiler optimizations for parallelizing general-purpose applications under thread-level speculation. PPoPP 2008: 271-272 - 2006
- [c10]Rao Fu, Jiwei Lu, Antonia Zhai, Wei-Chung Hsu:
A Study of the Performance Potential for Dynamic Instruction Hints Selection. Asia-Pacific Computer Systems Architecture Conference 2006: 67-80 - [c9]Abhinav Das, Rao Fu, Antonia Zhai, Wei-Chung Hsu:
Issues and Support for Dynamic Register Allocation. Asia-Pacific Computer Systems Architecture Conference 2006: 351-358 - [c8]Venkatesan Packirisamy, Shengyue Wang, Antonia Zhai, Wei-Chung Hsu
Supporting Speculative Multithreading on Simultaneous Multithreaded Processors. HiPC 2006: 148-158 - [c7]Shengyue Wang, Antonia Zhai, Pen-Chung Yew
Exploiting Speculative Thread-Level Parallelism in Data Compression Applications. LCPC 2006: 126-140 - 2005
- [j1]J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai, Todd C. Mowry:
The STAMPede approach to thread-level speculation. ACM Trans. Comput. Syst. 23(3): 253-300 (2005) - [c6]Xiaoru Dai, Antonia Zhai, Wei-Chung Hsu, Pen-Chung Yew:
A General Compiler Framework for Speculative Optimizations Using Data Speculative Code Motion. CGO 2005: 280-290 - [c5]Shengyue Wang, Xiaoru Dai, Kiran Yellajyosula, Antonia Zhai, Pen-Chung Yew
Loop Selection for Thread-Level Speculation. LCPC 2005: 289-303 - 2004
- [c4]Antonia Zhai, Christopher B. Colohan, J. Gregory Steffan, Todd C. Mowry:
Compiler Optimization of Memory-Resident Value Communication Between Speculative Threads. CGO 2004: 39-52 - 2002
- [c3]Antonia Zhai, Christopher B. Colohan, J. Gregory Steffan, Todd C. Mowry:
Compiler optimization of scalar value communication between speculative threads. ASPLOS 2002: 171-183 - [c2]J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai, Todd C. Mowry:
Improving Value Communication for Thread-Level Speculation. HPCA 2002: 65-75 - 2000
- [c1]J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai, Todd C. Mowry:
A scalable approach to thread-level speculation. ISCA 2000: 1-12
Coauthor Index
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last updated on 2024-09-13 01:42 CEST by the dblp team
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