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Brando Perez Esparza
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2020 – today
- 2021
- [j4]Jongseok Park
, Sushil Subramanian
A Fully Integrated Cryo-CMOS SoC for State Manipulation, Readout, and High-Speed Gate Pulsing of Spin Qubits. IEEE J. Solid State Circuits 56(11): 3289-3306 (2021) - [c3]Jong Seok Park, Sushil Subramanian, Lester Lampert, Todor Mladenov, Ilya Klotchkov, Dileep Kurian, Esdras Juárez-Hernández, Brando Perez Esparza, Sirisha Rani Kale, K. T. Asma Beevi, Shavindra P. Premaratne, Thomas Watson, Satoshi Suzuki, Mustafijur Rahman, Jaykant Timbadiya, Saksham Soni, Stefano Pellerano:
A Fully Integrated Cryo-CMOS SoC for Qubit Control in Quantum Computers Capable of State Manipulation, Readout and High-Speed Gate Pulsing of Spin Qubits in Intel 22nm FFL FinFET Technology. ISSCC 2021: 208-210 - 2020
- [j3]Jeroen Petrus Gerardus van Dijk
A Scalable Cryo-CMOS Controller for the Wideband Frequency-Multiplexed Control of Spin Qubits and Transmons. IEEE J. Solid State Circuits 55(11): 2930-2946 (2020) - [c2]Bishnu Patra
19.1 A Scalable Cryo-CMOS 2-to-20GHz Digitally Intensive Controller for 4×32 Frequency Multiplexed Spin Qubits/Transmons in 22nm FinFET Technology for Quantum Computers. ISSCC 2020: 304-306
2010 – 2019
- 2019
- [j2]Pascal Andreas Meinerzhagen
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. IEEE J. Solid State Circuits 54(1): 144-157 (2019) - 2018
- [c1]Pascal Meinerzhagen, Carlos Tokunaga
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. ISSCC 2018: 38-40
2000 – 2009
- 2007
- [j1]David Arditti Ilitzky, Jeffrey D. Hoffman, Anthony Chun, Brando Perez Esparza:
Architecture of the Scalable Communications Core's Network on Chip. IEEE Micro 27(5): 62-74 (2007)
Coauthor Index
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