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Dong-Jin Chang
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2020 – today
- 2022
- [j12]Sungho Suh
, Sojeong Cheon, Wonseo Choi
Supervised segmentation with domain adaptation for small sampled orbital CT images. J. Comput. Des. Eng. 9(2): 783-792 (2022) - [c5]Dong-Jin Chang, Seung-Tak Ryu:
A Relative-Prime Rotation Based Fully On-Chip Background Skew Calibration for Time-Interleaved ADCs. VLSI Technology and Circuits 2022: 174-175 - 2021
- [j11]Dong-Jin Chang
MixedNet: Network Design Strategies for Cost-Effective Quantized CNNs. IEEE Access 9: 117554-117564 (2021) - [j10]Tong Min Kim
Semi-AI and Full-AI digitizer: The ways to digitalize visual field big data. Comput. Methods Programs Biomed. 207: 106168 (2021) - [j9]Dong-Jin Chang
A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration. IEEE J. Solid State Circuits 56(9): 2691-2700 (2021) - [j8]Yongseok Mun
An innovative strategy for standardized, structured, and interoperable results in ophthalmic examinations. BMC Medical Informatics Decis. Mak. 21(1): 9 (2021) - [c4]Ye-Dam Kim
A 4th-order CT I-DSM with Digital Noise Coupling and Input Pre-conversion Method for Initialization. A-SSCC 2021: 1-3 - [c3]Seung-Yong Lim, Raymond Mabilangan, Dong-Jin Chang, Young-Jae Cho, Michael Choi, Seung-Tak Ryu:
An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation. A-SSCC 2021: 1-3 - [c2]Sungho Suh
Sequential Lung Nodule Synthesis Using Attribute-Guided Generative Adversarial Networks. MICCAI (6) 2021: 402-411 - [i1]Sungho Suh, Sojeong Cheon, Wonseo Choi, Yeon Woong Chung, Won-Kyung Cho, Ji-Sun Paik, Sung Eun Kim, Dong-Jin Chang, Yong Oh Lee:
Supervised Segmentation with Domain Adaptation for Small Sampled Orbital CT Images. CoRR abs/2107.00418 (2021) - 2020
- [j7]Yi-Ju Roh
A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision. IEEE Trans. Circuits Syst. 67-II(12): 2833-2837 (2020) - [j6]Dong-Jin Chang, Byeong-Gyu Nam
Compact Mixed-Signal Convolutional Neural Network Using a Single Modular Neuron. IEEE Trans. Circuits Syst. 67-I(12): 5189-5199 (2020)
2010 – 2019
- 2019
- [j5]Dong-Ryeol Oh
A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 $\times$ Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration. IEEE J. Solid State Circuits 54(1): 288-297 (2019) - [c1]Min-Jae Seo
A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability. A-SSCC 2019: 189-192 - 2018
- [j4]Dong-Jin Chang, Min-Jae Seo
A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration. IEEE Trans. Circuits Syst. II Express Briefs 65-II(3): 281-285 (2018) - [j3]Min-Jae Seo
A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1904-1908 (2018) - 2017
- [j2]Dong-Jin Chang, Wan Kim
Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(2): 322-332 (2017) - 2016
- [j1]Wan Kim
A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC. IEEE J. Solid State Circuits 51(8): 1826-1839 (2016)
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