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B. Sharat Chandra Varma 0001
Person information
- affiliation: Ulster University, Jordanstown, United Kingdom
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2020 – today
- 2024
- [c9]Cornell Castelino, Shashwat Khandelwal, Shanker Shreejith, Sharatchandra Varma Bogaraju:
An Energy-Efficient Artefact Detection Accelerator on FPGAs for Hyper-Spectral Satellite Imagery. DSD 2024: 551-558 - [i1]Cornell Castelino, Shashwat Khandelwal, Shanker Shreejith, Sharatchandra Varma Bogaraju:
An Energy-Efficient Artefact Detection Accelerator on FPGAs for Hyper-Spectral Satellite Imagery. CoRR abs/2407.17647 (2024) - 2022
- [j4]Sohan Lal
, Sharatchandra Varma Bogaraju, Ben H. H. Juurlink:
A Quantitative Study of Locality in GPU Caches for Memory-Divergent Workloads. Int. J. Parallel Program. 50(2): 189-216 (2022) - [j3]Maolin Wang
Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network. IEEE Trans. Neural Networks Learn. Syst. 33(7): 2853-2866 (2022)
2010 – 2019
- 2018
- [c8]Christoforos Kachris, Dimitrios Soudris
The VINEYARD integrated framework for hardware accelerators in the cloud. SAMOS 2018: 236-243 - 2017
- [j2]B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, Dominique Lavenier:
Hardware acceleration of de novo genome assembly. Int. J. Embed. Syst. 9(1): 74-89 (2017) - 2016
- [c7]Maolin Wang, Ho-Cheung Ng, Bob M. F. Chung, B. Sharat Chandra Varma, Manish Kumar Jaiswal, Kevin K. Tsia
Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA. FPT 2016: 261-264 - [c6]Ho-Cheung Ng, Maolin Wang, Bob M. F. Chung, B. Sharat Chandra Varma
High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform. ReConFig 2016: 1-6 - 2015
- [j1]Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So
Configurable Architectures for Multi-Mode Floating Point Adders. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2079-2090 (2015) - [c5]Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So
Architecture for Dual-Mode Quadruple Precision Floating Point Adder. ISVLSI 2015: 249-254 - 2014
- [c4]B. Sharat Chandra Varma
High Level Design Approach to Accelerate De Novo Genome Assembly Using FPGAs. DSD 2014: 66-73 - [c3]B. Sharat Chandra Varma
Accelerating Genome Assembly Using Hard Embedded Blocks in FPGAs. VLSID 2014: 306-311 - 2013
- [c2]B. Sharat Chandra Varma
FAssem: FPGA Based Acceleration of De Novo Genome Assembly. FCCM 2013: 173-176 - [c1]B. Sharat Chandra Varma
Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs. VLSI Design 2013: 92-97
Coauthor Index
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