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2020 – today
- 2022
- [j32]M. Balakrishnan:
Computing and assistive technology solutions for the visually impaired. Commun. ACM 65(11): 44-47 (2022) - [c92]Shikha Goel, Rajesh Kedia, Rijurekha Sen, M. Balakrishnan:
EXPRESS: CNN EXecution Time PREdiction for DPU DeSign Space Exploration. FPT 2022: 1-2 - [c91]Vikas Upadhyay, Kashi Roy, M. Balakrishnan:
Beacon Placement and Signal Strength Estimation to Improve Localization Coverage and Accuracy. IPIN 2022: 1-8 - 2021
- [j31]Rajesh Kedia
, Shikha Goel, M. Balakrishnan, Kolin Paul, Rijurekha Sen:
Design Space Exploration of FPGA-Based System With Multiple DNN Accelerators. IEEE Embed. Syst. Lett. 13(3): 114-117 (2021) - [j30]Solomon Abera, M. Balakrishnan, Anshul Kumar:
Performance-Energy Trade-off in Modern CMPs. ACM Trans. Archit. Code Optim. 18(1): 3:1-3:26 (2021) - [c90]M. Balakrishnan:
ASSISTECH: An Accidental Journey into Assistive Technology. A Journey of Embedded and Cyber-Physical Systems 2021: 57-77 - [c89]Shikha Goel, M. Balakrishnan, Rijurekha Sen:
EnergyNN: Energy Estimation for Neural Network Inference Tasks on DPU. FPL 2021: 64-68 - [c88]Anupam Sobti, Vaibhav Mavi, M. Balakrishnan, Chetan Arora:
VmAP: A Fair Metric for Video Object Detection. ACM Multimedia 2021: 2224-2232 - 2020
- [c87]Balasamy Krishnasamy
A Genetic Algorithm Based Medical Image Watermarking for Improving Robustness and Fidelity in Wavelet Domain. FICTA (2) 2020: 289-299 - [c86]Shikha Goel, Rajesh Kedia, M. Balakrishnan, Rijurekha Sen:
INFER: INterFerence-aware Estimation of Runtime for Concurrent CNN Execution on DPUs. FPT 2020: 66-71
2010 – 2019
- 2019
- [j29]Rajeswari Devadoss
Equivalence Checking and Compaction of n-input Majority Terms Using Implicants of Majority. J. Electron. Test. 35(5): 679-694 (2019) - [c85]Rajesh Kedia, M. Balakrishnan, Kolin Paul:
A case for design space exploration of context-aware adaptive embedded systems: work-in-progress. CODES+ISSS 2019: 12:1-12:2 - [c84]Rajesh Kedia, M. Balakrishnan, Kolin Paul:
GRanDE: Graphical Representation and Design Space Exploration of Embedded Systems. DSD 2019: 4-12 - [c83]Anupam Sobti, M. Balakrishnan, Chetan Arora:
Multi-sensor Energy Efficient Obstacle Detection. DSD 2019: 19-26 - [c82]Richa Gupta
Evaluating the Use of Variable Height in Tactile Graphics. WHC 2019: 121-126 - [c81]Solomon Abera Bekele, M. Balakrishnan, Anshul Kumar:
ML Guided Energy-Performance Trade-Off Estimation For Uncore Frequency Scaling. SpringSim 2019: 1-12 - [c80]Rajesh Kedia, Anupam Sobti, Mukund Rungta, Sarvesh Chandoliya, Akhil Soni, Anil Kumar Meena, Chrystle Myrna Lobo, Richa Verma, M. Balakrishnan, Chetan Arora:
MAVI: Mobility Assistant for Visually Impaired with Optional Use of Local and Cloud Resources. VLSID 2019: 227-232 - [c79]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
Majority Logic: Prime Implicants and n-Input Majority Term Equivalence. VLSID 2019: 464-469 - 2018
- [j28]Gayathri Ananthanarayanan, Smruti R. Sarangi, M. Balakrishnan:
Task Assignment Algorithms for Multicore Platforms with Process Variations. J. Low Power Electron. 14(2): 302-317 (2018) - [c78]Solomon Abera, M. Balakrishnan, Anshul Kumar:
Performance-Energy Trade-off in CMPs with Per-Core DVFS. ARCS 2018: 225-238 - [c77]Suman Adhepalli Muralikrishnan, Pulkit Sapra, Saurabh Agrawal, Piyush Chanana, M. Balakrishnan, P. V. M. Rao:
FPGA-Based Controllers for Compact Low Power Refreshable Braille Display. ISVLSI 2018: 632-637 - [c76]Anupam Sobti, Chetan Arora, M. Balakrishnan:
Object Detection in Real-Time Systems: Going Beyond Precision. WACV 2018: 1020-1028 - 2017
- [j27]Mansureh Shahraki Moghaddam
Optimal mapping of program overlays onto many-core platforms with limited memory capacity. Des. Autom. Embed. Syst. 21(3-4): 173-194 (2017) - [j26]B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, Dominique Lavenier:
Hardware acceleration of de novo genome assembly. Int. J. Embed. Syst. 9(1): 74-89 (2017) - [c75]Solomon Abera, M. Balakrishnan, Anshul Kumar:
PLSS: A Scheduler for Multi-core Embedded Systems. ARCS 2017: 164-176 - [c74]Rajesh Kedia, K. K. Yoosuf, Pappireddy Dedeepya, Munib Fazal, Chetan Arora, M. Balakrishnan:
MAVI: An Embedded Device to Assist Mobility of Visually Impaired. VLSID 2017: 213-218 - 2016
- [c73]Gayathri Ananthanarayanan, Smruti R. Sarangi, M. Balakrishnan:
Leakage Power Aware Task Assignment Algorithms for Multicore Platforms. ISVLSI 2016: 607-612 - 2015
- [j25]M. Balakrishnan, G. Marimuthu, S. Arumugam
Vertex in-magic arc labelings of digraphs. Electron. Notes Discret. Math. 48: 33-39 (2015) - [j24]S. Arumugam
E-Super Vertex In-Magic Total Labelings of Digraphs. Electron. Notes Discret. Math. 48: 111-118 (2015) - [j23]G. Marimuthu, S. Kavitha, M. Balakrishnan:
Super Edge Magic Graceful Labeling of Generalized Petersen Graphs. Electron. Notes Discret. Math. 48: 235-241 (2015) - [j22]Arun Parakh
Improving Map-Reduce for GPUs with cache. Int. J. High Perform. Syst. Archit. 5(3): 166-177 (2015) - [j21]Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So
Configurable Architectures for Multi-Mode Floating Point Adders. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2079-2090 (2015) - [c72]Mansureh Shahraki Moghaddam, M. Balakrishnan, Kolin Paul:
Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform. ARC 2015: 373-382 - 2014
- [j20]Manish Kumar Jaiswal, Ray C. C. Cheung
Series Expansion based Efficient Architectures for Double Precision Floating Point Division. Circuits Syst. Signal Process. 33(11): 3499-3526 (2014) - [j19]G. Marimuthu, M. Balakrishnan:
Super edge magic graceful graphs. Inf. Sci. 287: 140-151 (2014) - [j18]Manish Kumar Jaiswal, Ray C. C. Cheung
Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder. IEEE Trans. Circuits Syst. II Express Briefs 61-II(7): 521-525 (2014) - [c71]Smruti R. Sarangi, Gayathri Ananthanarayanan, M. Balakrishnan:
LightSim: A leakage aware ultrafast temperature simulator. ASP-DAC 2014: 855-860 - [c70]B. Sharat Chandra Varma
High Level Design Approach to Accelerate De Novo Genome Assembly Using FPGAs. DSD 2014: 66-73 - [c69]Mansureh Shahraki Moghaddam, Kolin Paul, M. Balakrishnan:
Mapping Tasks to a Dynamically Reconfigurable Coarse Grained Array. FCCM 2014: 33 - [c68]Mrinal Mech, Kunal Kwatra, Supriya Das, Piyush Chanana, Rohan Paul, M. Balakrishnan:
Edutactile - A Tool for Rapid Generation of Accurate Guideline-Compliant Tactile Graphics for Science and Mathematics. ICCHP (2) 2014: 34-41 - [c67]Manish Kumar Jaiswal, Ray C. C. Cheung
Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division. ISVLSI 2014: 332-337 - [c66]B. Sharat Chandra Varma
Accelerating Genome Assembly Using Hard Embedded Blocks in FPGAs. VLSID 2014: 306-311 - 2013
- [j17]Gayathri Ananthanarayanan, Geetika Malhotra, M. Balakrishnan, Smruti R. Sarangi:
Amdahl's law in the era of process variation. Int. J. High Perform. Syst. Archit. 4(4): 218-230 (2013) - [c65]Dhruv Jain, Akhil Jain, Rohan Paul, Akhila Komarika, M. Balakrishnan:
A path-guided audio based indoor navigation system for persons with visual impairment. ASSETS 2013: 33:1-33:2 - [c64]B. Sharat Chandra Varma
FAssem: FPGA Based Acceleration of De Novo Genome Assembly. FCCM 2013: 173-176 - [c63]Mansureh Shahraki Moghaddam, Kolin Paul, M. Balakrishnan:
Design and Implementation of High Performance Architectures with Partially Reconfigurable CGRAs. IPDPS Workshops 2013: 202-211 - [c62]B. Sharat Chandra Varma
Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs. VLSI Design 2013: 92-97 - 2012
- [j16]G. Marimuthu, M. Balakrishnan:
E-super vertex magic labelings of graphs. Discret. Appl. Math. 160(12): 1766-1774 (2012) - [j15]Sonali Chouhan, M. Balakrishnan, Ranjan Bose:
System-Level Design Space Exploration Methodology for Energy-Efficient Sensor Node Configurations: An Experimental Validation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(4): 586-596 (2012) - [j14]M. Balakrishnan, Hong Huang, Rafael Asorey-Cacheda
Measures and Countermeasures for Null Frequency Jamming of On-Demand Routing Protocols in Wireless Ad Hoc Networks. IEEE Trans. Wirel. Commun. 11(11): 3860-3868 (2012) - [c61]M. Balakrishnan:
Power Consumption in Multi-core Processors. IC3 2012: 3 - [c60]Arun Parakh
Performance Estimation of GPUs with Cache. IPDPS Workshops 2012: 2384-2393 - 2011
- [j13]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
p-QCA: A Tiled Programmable Fabric Architecture Using Molecular Quantum-Dot Cellular Automata. ACM J. Emerg. Technol. Comput. Syst. 7(3): 13:1-13:20 (2011) - [j12]Preeti Ranjan Panda, M. Balakrishnan, Anant Vishnoi:
Compressing Cache State for Postsilicon Processor Debug. IEEE Trans. Computers 60(4): 484-497 (2011) - [c59]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
Architecture and tools for programmable QCA. FPT 2011: 1-4 - 2010
- [c58]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
A tiled programmable fabric using QCA. FPT 2010: 9-16 - [c57]Preeti Ranjan Panda, Anant Vishnoi, M. Balakrishnan:
Enhancing post-silicon processor debug with Incremental Cache state Dumping. VLSI-SoC 2010: 55-60 - [c56]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
Clocking-Based Coplanar Wire Crossing Scheme for QCA. VLSI Design 2010: 339-344
2000 – 2009
- 2009
- [j11]Sonali Chouhan, Ranjan Bose, M. Balakrishnan:
A Framework for Energy-Consumption-Based Design Space Exploration for Wireless Sensor Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(7): 1017-1024 (2009) - [j10]Sonali Chouhan, Ranjan Bose, M. Balakrishnan:
Integrated energy analysis of error correcting codes and modulation for energy efficient wireless sensor nodes. IEEE Trans. Wirel. Commun. 8(10): 5348-5355 (2009) - [c55]Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan:
Online cache state dumping for processor debug. DAC 2009: 358-363 - [c54]Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan:
Cache aware compression for processor debug support. DATE 2009: 208-213 - [c53]Aryabartta Sahu
A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors. DATE 2009: 1018-1023 - [c52]Sonali Chouhan, M. Balakrishnan, Ranjan Bose:
An experimental validation of system level design space exploration methodology for energy efficient sensor nodes. ISLPED 2009: 355-358 - 2008
- [c51]Sonali Chouhan, M. Balakrishnan, Ranjan Bose:
A framework for energy consumption based design space exploration for wireless sensor nodes. ISLPED 2008: 329-334 - 2007
- [j9]Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar:
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. Int. J. Parallel Program. 35(6): 507-527 (2007) - [j8]Anup Gangwar, M. Balakrishnan, Anshul Kumar:
Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures. ACM Trans. Design Autom. Electr. Syst. 12(1): 1:1-1:29 (2007) - [c50]Ashutosh Pal, M. Balakrishnan:
A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures. FPL 2007: 517-520 - [c49]M. Balakrishnan, N. Ravisankar, K. Meena, R. Elanchezhian, S. K. Zamir Ahmed:
Yield Prediction Through Feed Forward Neural Network Approach for Direct Seeded Rice (Oryza sativa) in Bay Islands. IICAI 2007: 1533-1541 - 2006
- [c48]Harsh Dhand, Basant Kumar Dwivedi, M. Balakrishnan:
New approach to architectural synthesis: incorporating QoS constraint. EMSOFT 2006: 301-310 - [c47]Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrishnan, Anshul Kumar:
Rapid Resource-Constrained Hardware Performance Estimation. IEEE International Workshop on Rapid System Prototyping 2006: 40-46 - [c46]Anmol Mathur, Masahiro Fujita, M. Balakrishnan, Raj S. Mitra:
Sequential Equivalence Checking. VLSI Design 2006: 18-19 - 2005
- [c45]Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar:
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. DATE 2005: 730-735 - [c44]Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, Subhashis Banerjee:
SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only). FPGA 2005: 273 - [c43]M. Balakrishnan, B. S. Panwar:
A Specialized Graduate Program in VLSI Design Tools and Technology. MSE 2005: 83-84 - [c42]Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar:
Integrated On-Chip Storage Evaluation in ASIP Synthesis. VLSI Design 2005: 274-279 - [c41]Gaurav Arora, Abhishek Sharma, D. Nagchoudhuri, M. Balakrishnan:
ADOPT: An Approach to Activity Based Delay Optimization. VLSI Design 2005: 411-416 - 2004
- [j7]Manoj Kumar Jain
An efficient technique for exploring register file size in ASIP design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12): 1693-1699 (2004) - [c40]Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan:
Automatic synthesis of system on chip multiprocessor architectures for process networks. CODES+ISSS 2004: 60-65 - [c39]Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan:
Synthesis of Application Specific Multiprocessor Architectures for Process Networks. VLSI Design 2004: 780-783 - 2003
- [c38]Manoj Kumar Jain
Exploring Storage Organization in ASIP Synthesis. DSD 2003: 120-127 - [c37]Amarjeet Singh, Amit Chhabra, Anup Gangwar, Basant Kumar Dwivedi, M. Balakrishnan, Anshul Kumar:
SoC Synthesis with Automatic Hardware Software Interface Generation. VLSI Design 2003: 585- - 2002
- [c36]Manoj Kumar Jain
An efficient technique for exploring register file size in ASIP synthesis. CASES 2002: 252-261 - [c35]Rajeshwari Banakar, Stefan Steinke, Bo-Sik Lee, M. Balakrishnan, Peter Marwedel:
Scratchpad memory: design alternative for cache on-chip memory in embedded systems. CODES 2002: 73-78 - [c34]M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha:
A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. ISSS 2002: 2-7 - [c33]M. Balakrishnan, Anshul Kumar, C. P. Joshi:
A New Performance Evaluation Approach for System Level Design Space Exploration. ISSS 2002: 180-185 - [c32]M. Balakrishnan, Peter Marwedel, Lars Wehmeyer, Nils Grunwald, Rajeshwari Banakar
Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip Memory. ISSS 2002: 213-218 - [c31]Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar:
Exploring the Number of Register Windows in ASIP Synthesis. ASP-DAC/VLSI Design 2002: 233-238 - [c30]Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan:
A New Divide and Conquer Method for Achieving High Speed Division in Hardware. ASP-DAC/VLSI Design 2002: 535-540 - 2001
- [j6]Lars Wehmeyer, Manoj Kumar Jain
Analysis of the influence of register file size on energyconsumption, code size, and execution time. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(11): 1329-1337 (2001) - [c29]Basant Kumar Dwivedi, Jan Hoogerbrugge, Paul Stravers, M. Balakrishnan:
Exploring design space of parallel realizations: MPEG-2 decoder case study. CODES 2001: 92-97 - [c28]Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, Peter Marwedel, M. Balakrishnan:
Evaluating register file size in ASIP design. CODES 2001: 109-114 - [c27]M. Balakrishnan:
A Specialized Graduate Program in VLSI Design: A Success Story. MSE 2001: 85-86 - [c26]Anupam Rastogi, M. Balakrishnan, Anshul Kumar:
Integrating Communication Cost Estimation in Embedded Systems Design : A PCI Case Study. VLSI Design 2001: 23-28 - [c25]Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar:
ASIP Design Methodologies : Survey and Issues. VLSI Design 2001: 76- - 2000
- [j5]M. Balakrishnan, Heman Khanna:
Allocation of FIFO structures in RTL data paths. ACM Trans. Design Autom. Electr. Syst. 5(3): 294-310 (2000) - [c24]Akshaye Sama, J. F. M. Theeuwen, M. Balakrishnan:
Speeding up power estimation of embedded software. ISLPED 2000: 191-196 - [c23]Arvind Rajawat, M. Balakrishnan, Anshul Kumar:
nterface Synthesis: Issues and Approaches. VLSI Design 2000: 92 - [c22]T. Vinod Kumar Gupta, Purvesh Sharma, M. Balakrishnan, Sharad Malik
Processor Evaluation in an Embedded Systems Design Environment. VLSI Design 2000: 98-103 - [c21]Aviral Shrivastava, Mohit Kumar, Sanjiv Kapoor, Shashi Kumar, M. Balakrishnan:
Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming. VLSI Design 2000: 110-113
1990 – 1999
- 1999
- [c20]M. Anand, Sanjiv Kapoor, M. Balakrishnan:
Hardware/Software Partitioning Between Microprocessor and Reconfigurable Hardware. FPGA 1999: 249 - [c19]Rashmi Goswami, V. Srinivasan, M. Balakrishnan:
MPEG-2 Video Data Simulator: A Case Study in Constrained HW-SW Codesign. VLSI Design 1999: 128-132 - [c18]Ajoy C. Siddabathuni, M. Balakrishnan:
Simulation and Modeling of a Multicast ATM Switch. VLSI Design 1999: 242- - 1998
- [j4]A. R. Naseer, M. Balakrishnan, Anshul Kumar:
Direct mapping of RTL structures onto LUT-based FPGA's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(7): 624-631 (1998) - [c17]Sandeep K. Lodha, Shashank Gupta, M. Balakrishnan, Subhashis Banerjee:
Real Time Collision Detection and Avoidance: A Case Study for Design Space Exploration in HW-SW Codesign. VLSI Design 1998: 97- - [c16]Sitanshu Jain, M. Balakrishnan, Anshul Kumar, Shashi Kumar:
Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library. VLSI Design 1998: 400-405 - 1997
- [c15]Heman Khanna, M. Balakrishnan:
Allocation of FIFO Structures in RTL Data Paths. VLSI Design 1997: 130-133 - [c14]A. R. Naseer, M. Balakrishnan, Anshul Kumar:
Optimal Clock Period for Synthesized Data Paths. VLSI Design 1997: 134-139 - [c13]Gaurav Aggarwal, Nitin Thaper, Kamal Aggarwal, M. Balakrishnan, Shashi Kumar:
A Novel Reconfigurable Co-Processor Architecture. VLSI Design 1997: 370-375 - 1995
- [c12]A. R. Naseer, M. Balakrishnan, Anshul Kumar:
Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs. FPL 1995: 139-148 - [c11]M. Balakrishnan:
Buffer constraints in a variable-rate packetized video system. ICIP 1995: 29-32 - [c10]Alok Kumar, Anshul Kumar, M. Balakrishnan:
Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis. VLSI Design 1995: 75-80 - 1994
- [c9]A. R. Naseer, M. Balakrishnan, Anshul Kumar:
An Efficient Technique for Mapping RTL Structures onto FPGAs. FPL 1994: 99-110 - [c8]Atul Varshneya, B. B. Madan, M. Balakrishnan:
Concurrent Search and Insertion in K-Dimensional Height Balanced Trees. IPPS 1994: 883-887 - [c7]A. R. Naseer, M. Balakrishnan, Anshul Kumar:
FAST: FPGA Targeted RTL Structure Synthesis Technique. VLSI Design 1994: 21-24 - 1993
- [c6]C. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer:
High Level Design Experiences with IDEAS. VLSI Design 1993: 110 - [c5]M. V. Rao, M. Balakrishnan, Anshul Kumar:
DESSERT: Design Space Exploration of RT Level Components. VLSI Design 1993: 299-304 - 1992
- [c4]Prashant P. Nedungadi, M. Balakrishnan, Anshul Kumar:
Data Path Synthesis With Global Time Constraint. VLSI Design 1992: 322-323
1980 – 1989
- 1989
- [c3]M. Balakrishnan, Peter Marwedel:
Integrated Scheduling and Binding: A Synthesis Approach for Design Space Exploration. DAC 1989: 68-74 - 1988
- [j3]M. Balakrishnan, S. Sutarwala, Arun K. Majumdar, Dilip K. Banerji, James G. Linders:
A Semantic Approach for Modular Synthesis of VLSI Systems. Inf. Process. Lett. 27(1): 1-7 (1988) - [j2]M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders:
Synthesis of decentralised controllers from high level description. Microprocess. Microprogramming 22(3): 217-229 (1988) - [j1]M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders, Jayanti C. Majithia:
Allocation of multiport memories in data path synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(4): 536-540 (1988) - 1986
- [c2]M. Balakrishnan, P. C. P. Bhatt, B. B. Madan:
An efficient retargetable microcode generator. MICRO 1986: 44-53 - 1982
- [c1]M. Balakrishnan, A. V. S. M. Rao, Rajendar Bahl:
A multi-channel microprogrammed FFT processor. ICASSP 1982: 492-497
Coauthor Index
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