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Yu Deng 0001
Person information
- affiliation: National University of Defense Technology, School of Computer, Changsha, China
Other persons with the same name
- Yu Deng — disambiguation page
- Yu Deng 0002 — Chinese Academy of Sciences, Institute of Geographic Sciences and Natural Resources Research, Beijing, China
- Yu Deng 0003
— Tsinghua University, Department of Electronic Engineering, Beijing, China (and 1 more)
- Yu Deng 0004 — IBM, T.J. Watson Research Center, Yorktown Heights, USA (and 1 more)
- Yu Deng 0005 — King's College London, Department of Biomedical Engineering, UK
- Yu Deng 0006
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2020 – today
- 2020
- [j7]Zikai Nie, Zhisheng Li, Lei Wang, Shasha Guo, Yu Deng, Rangyu Deng, Qiang Dou:
Laius: an energy-efficient FPGA CNN accelerator with the support of a fixed-point training framework. Int. J. Comput. Sci. Eng. 21(3): 418-428 (2020) - [j6]Shuquan Wang, Lei Wang, Yu Deng, Zhi-Jie Yang
SIES: A Novel Implementation of Spiking Convolutional Neural Network Inference Engine on Field-Programmable Gate Array. J. Comput. Sci. Technol. 35(2): 475-489 (2020) - [j5]Lei Wang
CSMO-DSE: Fast and Precise Application-driven DSE Guided by Criticality and Sensitivity Analysis. ACM J. Emerg. Technol. Comput. Syst. 16(2): 16:1-16:22 (2020) - [j4]Ziyang Kang
ASIE: An Asynchronous SNN Inference Engine for AER Events Processing. ACM J. Emerg. Technol. Comput. Syst. 16(4): 39:1-39:22 (2020)
2010 – 2019
- 2019
- [c20]Ziyang Kang
ASIE: An Asynchronous SNN Inference Engine for AER Events Processing. ASYNC 2019: 48-57 - [c19]Shasha Guo, Lei Wang, Shuquan Wang, Yu Deng, Zhijie Yang
A Systolic SNN Inference Accelerator and its Co-optimized Software Framework. ACM Great Lakes Symposium on VLSI 2019: 63-68 - 2018
- [c18]Shuquan Wang, Shasha Guo, Lei Wang, Nan Li, Zikai Nie, Yu Deng, Qiang Dou, Weixia Xu:
A Power Efficient Hardware Implementation of the IF Neuron Model. ACA 2018: 140-154 - [c17]Lei Wang, Yu Deng, Rui Gong, Wei Shi, Zhenyu Zhao, Qiang Dou:
A Parallel Algorithm for Instruction Dependence Graph Analysis Based on Multithreading. ISPA/IUCC/BDCloud/SocialCom/SustainCom 2018: 716-721 - [c16]Zhijie Yang
Systolic Array Based Accelerator and Algorithm Mapping for Deep Learning Algorithms. NPC 2018: 153-158 - 2017
- [c15]Zhisheng Li, Lei Wang, Shasha Guo, Yu Deng, Qiang Dou, Haifang Zhou, Wenyuan Lu:
Laius: An 8-Bit Fixed-Point CNN Hardware Inference Engine. ISPA/IUCC 2017: 143-150 - 2016
- [c14]Yuxing Tang, Lei Wang, Yu Deng, Xiaoqiang Ni, Qiang Dou:
The Macro-DSE for HPC Processing Unit: The Physical Constraints Perspective. GPC 2016: 99-112 - 2015
- [c13]Lei Wang, Yuxing Tang, Yu Deng, Fangyan Qin, Qiang Dou, Guangda Zhang, Feipeng Zhang:
A Scalable and Fast Microprocessor Design Space Exploration Methodology. MCSoC 2015: 33-40
2000 – 2009
- 2009
- [j3]Xuejun Yang, Yu Deng, Li Wang, Xiaobo Yan, Jing Du, Ying Zhang, Guibin Wang, Tao Tang:
SRF Coloring: Stream Register File Allocation via Graph Coloring. J. Comput. Sci. Technol. 24(1): 152-164 (2009) - [j2]Xuejun Yang, Jing Du, Xiaobo Yan, Yu Deng:
Matrix-based streamization approach for improving locality and parallelism on FT64 stream processor. J. Supercomput. 47(2): 171-197 (2009) - [j1]Xuejun Yang, Xiaobo Yan, Zuocheng Xing, Yu Deng, Jiang Jiang, Jing Du, Ying Zhang:
Fei Teng 64 Stream Processing System: Architecture, Compiler, and Programming. IEEE Trans. Parallel Distributed Syst. 20(8): 1142-1157 (2009) - [c12]Xuejun Yang, Li Wang, Jingling Xue
Comparability graph coloring for optimizing utilization of stream register files in stream processors. PPoPP 2009: 111-120 - 2008
- [c11]Yu Deng, Li Wang, Xiaobo Yan, Xuejun Yang:
A Double-Buffering Strategy for the SRF management in the Imagine Stream Processor. ICYCS 2008: 160-165 - [c10]Ying Zhang, Xuejun Yang, Guibin Wang, Ian Rogers, Gen Li, Yu Deng, Xiaobo Yan:
Scientific Computing Applications on a Stream Processor. ISPASS 2008: 105-114 - [c9]Li Wang, Xuejun Yang, Jingling Xue
Optimizing scientific application loops on stream processors. LCTES 2008: 161-170 - 2007
- [c8]Yu Deng, Xuejun Yang, Xiaobo Yan, Ying Zhang, Jing Du:
Implementation and Evaluation of Specific Data-Intensive Scientific Applications on the FT64 Stream Processor. CIT 2007: 339-343 - [c7]Yu Deng, Xuejun Yang, Xiaobo Yan, Kun Zeng:
Laplace Transformation on the FT64 Stream Processor. Asia-Pacific Computer Systems Architecture Conference 2007: 52-62 - [c6]Xuejun Yang, Yu Deng, Xiaobo Yan, Li Wang, Jing Du, Ying Zhang:
Efficient generation of stream programs from loops. ICPADS 2007: 1-8 - [c5]Xiaobo Yan, Tao Tang, Yu Deng, Jing Du, Xuejun Yang:
Evaluation of Transcendental Functions on Imagine Architecture. ICPP 2007: 53 - [c4]Xuejun Yang, Xiaobo Yan, Zuocheng Xing, Yu Deng, Jiang Jiang, Ying Zhang:
A 64-bit stream processor architecture for scientific applications. ISCA 2007: 210-219 - [c3]Li Wang, Xuejun Yang, Guibin Wang, Xiaobo Yan, Yu Deng, Jing Du, Ying Zhang, Tao Tang, Kun Zeng:
Implementation and Optimization of Sparse Matrix-Vector Multiplication on Imagine Stream Processor. ISPA 2007: 44-55 - 2006
- [c2]Xuejun Yang, Jing Du, Xiaobo Yan, Yu Deng:
Matrix-Based Programming Optimization for Improving Memory Hierarchy Performance on Imagine. ISPA 2006: 782-793 - 2004
- [c1]Guanghui Liu, Fei Xia, Xuejun Yang, Haifang Zhou, Heng Zhao, Yu Deng:
The Design and Performance Analysis of Embedded Parallel Multiprocessing System. ICESS 2004: 210-215
Coauthor Index
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