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Microelectronics Journal, Volume 60
Volume 60, February 2017
- Mrinal Goswami
, Bibhash Sen, Rijoy Mukherjee, Biplab K. Sikdar
Design of Testable Adder in Quantum-dot Cellular Automata with Fault Secure Logic. 1-12 - Thomas Souvignet, Bruno Allard, Alexandre Mas:
A compact implementation of a negative switched-capacitor voltage regulator dedicated to body-biasing of CMOS circuits. 13-20 - Paul Jung-Ho Lee, Man Kay Law, Amine Bermak
Global digital controller for multi-channel micro-stimulator with 5-wire interface featuring on-the-fly power-supply modulation and tissue impedance monitoring. 21-29 - Reshma P. G., Varun P. Gopi
Analog CMOS implementation of FFT using cascode current mirror. 30-37 - Wen-Hui Huang, I-Yu Huang, Yu-Shan Tseng, Chia-Hsu Hsieh
A 19.38 dBm OIP3 gm-boosted up-conversion CMOS mixer for 5-6 GHz application. 38-44 - Young Jun Park, Fei Yuan:
Two-step pulse-shrinking time-to-digital converter. 45-54 - Jingwei Li, Shiwei Feng, Yamin Zhang, Chao Wang, Xin He:
Optimized thermal sensor allocation for field-programmable gate array temperature measurements based on self-heating test. 55-59 - Seyed Amin Alavi, Saman Ghadirian, Seyyed Javad Seyyed Mahdavi Chabok
Bandwidth and gain extension technique for CMOS distributed amplifiers using negative capacitance and resistance cell. 60-64 - Jie Zhang, Hong Zhang, Jiangtao Xu, Yang Zhao, Jia Li, Guoyu Hu, Jialu Wang, Ruizhi Zhang, Yong Lian
A low energy ASIC for triple-chamber cardiac pacemakers with contact resistance measurement. 65-74 - Menghui Zhi, Quan Sun, Donghai Qiao:
A scalable decimation filter ASIC for high resolution digital magnetometer with sigma-delta modulator feedback loop. 75-81 - Jose Carlos Garcia-Montesdeoca, Juan A. Montiel-Nelson, Saeid Nooshabadi:
High performance single supply CMOS 0.45-1 V input to 1.1 V output level up shifter. 82-86 - Jinwoo Lee, Daeil Kwon:
A digital technique for diagnosing interconnect degradation by using digital signal characteristics. 87-93 - A. N. Ragheb
Ultra-low power OTA based on bias recycling and subthreshold operation with phase margin enhancement. 94-101 - Lianxi Liu, Yu Song, Junchao Mu, Wei Guo, Zhangming Zhu, Yintang Yang:
A high accuracy CMOS subthreshold voltage reference with offset cancellation and thermal compensation. 102-108 - Hossam Sarhan, Sébastien Thuries, Olivier Billoint, Fabien Clermidy:
Cell-on-Buffer: New design approach for high-performance and low-power monolithic 3D integrated circuits. 109-118 - Rajeev K. Ranjan, Nishtha Rani, Ratnadeep Pal, Sajal K. Paul, Gaurav Kanyal:
Single CCTA based high frequency floating and grounded type of incremental/decremental memristor emulator and its application. 119-128 - César A. M. Marcon
Models of computation for NoC mapping: Timing and energy saving awareness. 129-143
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