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SoCC 2009: Belfast, Northern Ireland, UK
- Annual IEEE International SoC Conference, SoCC 2009, September 9-11, 2009, Belfast, Northern Ireland, UK, Proceedings. IEEE 2009, ISBN 978-1-4244-4940-8
Plenary Session
- Hermann Eul:
Keynote speaker. 3-4 - James O'Riordan:
Plenary presentation A. 5 - Liang-Gee Chen:
Plenary presentation B. 6
Session WA1: FPGA Design Methodologies
- Wayne Luk, José Gabriel de Figueiredo Coutinho, Timothy John Todman, Yuet Ming Lam, William George Osborne, Kong Woei Susanto, Qiang Liu, W. S. Wong:
A high-level compilation toolchain for heterogeneous systems. 9-18 - Maurizio Tranchero, Leonardo Maria Reyneri:
A multi-level simulation approach in a Simulink-based design tool for FPGAs. 19-22 - Joseph M. Lancaster, Jeremy D. Buhler
, Roger D. Chamberlain:
Efficient runtime performance monitoring of FPGA-based applications. 23-28 - Süleyman Sirri Demirsoy, Kellie Marks:
SoC framework for FPGA: A case study of LTE PUSCH receiver. 29-32
Session WA2 - PLL and Clocks
- Saiyu Ren, Ray Siferd:
Performance comparison of two low power wide tuning range VCOs in 90 nm CMOS. 35-38 - Ping Lu, Danfeng Chen, Fan Ye
A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator. 39-42 - Nan Xing, Heesoo Song, Deog-Kyoon Jeong, Suhwan Kim:
A PVT-insensitive time-to-digital converter using fractional difference Vernier delay lines. 43-46 - Marta Blaszczyk, Richard A. Guinee:
Hardware implementation on PCB in tandem with FPGA and experimental validation of a novel true random binary generator. 47-50 - Chorng-Sii Hwang, Chun-Yung Cho, Chung-Chun Chen, Hen-Wai Tsao
Dual-band CDR using a half-rate linear phase detector. 51-54
Session WA3 - Reconfigurable Architectures
- Xin Zhao, Ahmet T. Erdogan
A novel high-efficiency partial-parallel context modeling architecture for EBCOT in JPEG2000. 57-60 - Chun Hok Ho, Wayne Luk, Jakub Szefer, Ruby B. Lee:
Tuning instruction customisation for reconfigurable system-on-chip. 61-64 - Mahtab Niknahad, Michael Hübner, Jürgen Becker:
Method for improving performance in online routing of reconfigurable nano architectures. 65-68
Session WB1 - A/D Converters
- Yan Wang, Gabor C. Temes:
Low-distortion double-sampling ΔΣ ADC using a direct-charge-transfer adder. 71-74 - Dongheon Lee, Seunghun Kim, Jooho Hwang, Junho Moon, Minkyu Song:
Design of a 1.8V 8-bit 1GSPS cascaded-folding CMOS A/D converter based on a folder averaging technique. 79-82 - Manho Kim, Nan Xing, Dong-Yong Shin, Hyunjoong Lee, Suhwan Kim:
A high resolution capacitance deviation-to-digital converter utilizing time stretching. 83-86
Session WB2 - Embedded Systems, Multi Core, and Embedded Memory
- Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres:
Adaptive energy-aware latency-constrained DVFS policy for MPSoC. 89-92 - Vassilios A. Chouliaras, Konstantinos Manolopoulos, Dionysios I. Reisis:
A configurable length, Fused Multiply-Add floating point unit for a VLIW processor. 93-96 - Wei Han, Ying Yi, Xin Zhao, Mark Muir, Tughrul Arslan, Ahmet T. Erdogan
Heterogeneous multi-core architectures with dynamically reconfigurable processors for WiMAX transmitter. 97-100 - Jihi-Yu Lin, Ming-Hsien Tu, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang:
Asymmetrical Write-assist for single-ended SRAM operation. 101-104
Session WB3 - Low-Power Circuits and Architectures
- Abhinav Kranti, G. Alastair Armstrong:
Improving Operational transconductance Amplifier (OTA) gain-bandwidth tradeoff using gate-underlap MOSFETs. 107-110 - Björn Lipka, Ulrich Kleine, Christoph Scheytt, Klaus Schmalz:
Design of a complementary folded-cascode operational amplifier. 111-114 - Yi-Ming Chang, Ming-Hung Chang, Wei Hwang:
A 2.1-mW 0.3V-1.0V wide locking range multiphase DLL using self-estimated SAR algorithm. 115-118 - Tung Thanh Hoang, Magnus Själander
High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture. 119-122
Session TA1 - Circuits for RF and Wireless
- Vincent F. Fusco, Chuang Wang:
54-65 GHz six port demodulator. 125-128 - Vincent F. Fusco, Chuang Wang:
Ultra wideband 32-67GHz phase shift keyed modulator. 129-132 - Tero Koivisto, Esa Tiiliharju:
A linearized low-voltage oscillator-mixer. 133-136 - Kai Xuan, Kim Fung Tsang
A current bleeding mixer based on Gilbert-cell featuring LO amplification. 137-140
Session TA2 - NoC Power and Data Flow Optimization
- Simon J. Hollis, Chris Jackson:
When does Network-on-Chip bypassing make sense? 143-146 - G. Vikas, Joy Kuri, Kuruvilla Varghese:
Power optimal Network-on-Chip interconnect design. 147-150 - Zhonghai Lu, Dimitris Brachos, Axel Jantsch
A flow regulator for On-Chip Communication. 151-154 - Mohamed A. Abd El-Ghany
High throughput architecture for CLICHÉ Network on Chip. 155-158
Session TA3 - Design for Testability and Verification
- Kuen-Jong Lee, Si-Yuan Liang, Alan P. Su:
A low-cost SOC debug platform based on on-chip test architectures. 161-164 - Cristian E. Onete
Comparator testing in a flash A/D converter. 165-168 - Brendan Mullane
A prototype platform for system-on-chip ADC test and measurement. 169-172 - Mariagrazia Graziano, Marco Diego Vittori:
A fully digital power supply noise thermometer. 173-176
Poster Session
Analog and Mixed Signals
- Seungwon Lee, Tae-Ho Kim, Jae-Wook Yoo, Jin-Ku Kang:
A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort in 0.18μm CMOS. 179-182 - Mahesh Kumar Adimulam, Sreehari Veeramachaneni
A novel low power, variable resolution pipelined ADC. 183-186 - P. Srinivasan
Correlating op-amp circuit noise with device flicker (1/f) noise for analog design applications. 191-194
RF and Wireless
- Marc Molina, Xavier Aragonès
Experimental analysis of substrate isolation techniques for RF-SOC integration. 199-202 - Chuang Wang, Vincent F. Fusco:
High-purity 56-66GHz quadrupler for V-band radio homodyne and heterodyne transceiver applications. 203-205
Embedded Systems, Multi Core, and Embedded Memory
- Jui-Chieh Lin, Minja Hsieh, Ming-Jung Fan-Chiang, Chu Yu, Sao-Jie Chen
An instruction set architecture independent design method for embedded OFDM-based software defined transmitter. 207-210 - Robert J. Ascott, Earl E. Swartzlander Jr.:
JavaFlow - A Java dataflow machine. 211-214 - Chander Sudanthi, Mrinmoy Ghosh, Kevin Welton, Nigel C. Paver:
Performance analysis of compressed instruction sets on workloads targeted at mobile internet devices. 215-218
Low Power
- Farshad Moradi
Improved write margin 6T-SRAM for low supply voltage applications. 223-226 - Jin-Tai Yan, Zhi-Wei Chen:
Low-power multiplier design with row and column bypassing. 227-230
Verification
- Younsun Kim, Hong-Sik Kim, R. Lee, Sungho Kang:
FPGA-based verification methodology of SoC-type CMOS image signal processor. 231-234
Audio and Video Processing
- Hui Geng, Weiqian Liang, Ming Dong:
A speech recognition SoC based on ARM7-TDMI core and a MSAC co-processor. 235-238 - Chun F. Hsu, Mong-Kai Ku, Li-Yen Liu:
Support vector machine FPGA implementation for video shot boundary detection application. 239-242
Network on Chip and Interconnect
- Shufan Yang, Stephen B. Furber
Adaptive admission control on the SpiNNaker MPSoC. 243-246 - Alexander Fell
Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT. 251-254 - Xiaofei Guo, Shunting Lin, Wael Refai
Non-overlapping transition encoding for global on-chip interconnect. 255-258 - Azeez Sanusi, Magdy A. Bayoumi:
Smart-flooding: A novel scheme for fault-tolerant NoCs. 259-262
System Level Design Methodology
- Philipp A. Hartmann
Modelling control systems in SystemC AMS - Benefits and limitations. 263-266 - Yang Sun, Joseph R. Cavallaro
Scalable and low power LDPC decoder design using high level algorithmic synthesis. 267-270
Reconfigurable and Programmable Circuits and Systems, FPGAs
- Saeed Fouladi Fard, Amirhossein Alimohammad, Bruce F. Cockburn, Christian Schlegel:
A versatile fading simulator for on-chip verification of MIMO communication systems. 271-274 - Ahmed O. El-Rayis, Xin Zhao, Tughrul Arslan, Ahmet T. Erdogan
Low power RS codec using cell-based reconfigurable processor. 279-282 - Arfan Ghani
Neuro inspired reconfigurable architecture for hardware/software co-design. 287-290
NEMS/MEMS Devices
- Ryoko Hayashi, Vijay K. Jain:
Capacitance change estimation for an immunosensor chip. 291-294 - Ambarish Roy, Bradley P. Barber, Kanti Prasad:
RF-MEMS resonator design for parameter characterization. 295-298
Session TB1 - Analog Circuit Techniques
- Franz Dielacher
A holistic design approach for systems on chip. 301-306 - Yngvar Berg, Omid Mirmotahari
Clocked semi-floating-gate ultra low-voltage inverting current mirror. 307-310 - Joona Marku, Jonne Poikonen, Ari Paasio
Temperature behavior of combination selection based mismatch calibration with 65 nm CMOS technology. 311-314 - Yngvar Berg, Omid Mirmotahari
Clocked semi-floating-gate ultra low-voltage symmetric and bidirectional current mirror. 315-318
Session TB2 - System Level Design for Manufacturing
- Iris Hui-Ru Jiang:
Generic integer linear programming formulation for 3D IC partitioning. 321-324 - Tariq E. L. Motassadeq, Vijay Sarathi, Syed Thameem, Mohamed Nijam:
SPICE versus STA tools: Challenges and tips for better correlation. 325-328 - Sheng Chou, Tsung-Yi Ho
OAL: An obstacle-aware legalization in standard cell placement with displacement minimization. 329-332 - Frank Rogin, Rolf Drechsler
Automatic debugging of System-on-a-Chip designs. 333-336 - Shinyu Ninomiya, Masanori Hashimoto
Enhancement of grid-based spatially-correlated variability modeling for improving SSTA accuracy. 337-340
Session TB3 - Data Processing Architectures
- Wei Wang, Weiqian Liang:
A reconfigurable co-processor for GMM-based classifier. 343-346 - Yongping Liu, Sakir Sezer, John V. McCanny:
NFA decomposition and multiprocessing architecture for parallel regular expression processing. 347-350 - Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns:
DDR3 based lookup circuit for high-performance network processing. 351-354
Session FA1 - Low-Power Design Methodologies and IP Cores
- Sohaib Majzoub
Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT. 357-360 - Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler:
Fast dynamic power estimation considering glitch filtering. 361-364 - Ashok Narasimhan, Ramalingam Sridhar:
Variation aware low power buffered interconnect design. 365-368 - Tom English, Maurice Keller, Ka Lok Man, Emanuel M. Popovici, Michel P. Schellekens, William P. Marnane
A low-power pairing-based cryptographic accelerator for embedded security applications. 369-372
Session FA2 - NoC Design Tools and Digital Signal Processing
- Po-Tsang Huang, Wei Hwang:
An adaptive congestion-aware routing algorithm for mesh network-on-chip platform. 375-378 - Mohammad Reza Kakoee, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Ciprian Seiculescu, Luca Benini
A floorplan-aware interactive tool flow for NoC design and synthesis. 379-382 - Nuo Li, Nick van der Meijs:
A Radix 22 based parallel pipeline FFT processor for MB-OFDM UWB system. 383-386 - Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.:
ASIC evaluation of ECHO hash function. 387-390
Session FB1 - System Level Architecture Exploration
- Moazzam Fareed Niazi, Khalid Latif, Hannu Tenhunen, Tiberiu Seceleanu
A DSL for the SegBus platform. 393-398 - Sumit Ahuja, Deepak Mathaikutty, Avinash Lakshminarayana, Sandeep K. Shukla
Accurate power estimation of hardware co-processors using system level simulation. 399-402 - Maurizio Tranchero, Leonardo Maria Reyneri:
Generating interacting synchronous and asynchronous designs from simulink descriptions. 403-406 - Hari Kannan, Mihai Budiu, John D. Davis, Girish Venkataramani:
Tuning SoCs using the global dynamic critical path. 407-411 - Saeed Fouladi Fard, Amirhossein Alimohammad, Bruce F. Cockburn, Christian Schlegel:
High path-count multirate Rayleigh fading channel simulator with time-multiplexed datapath. 412-415
Session FB2 - Imaging and Video Processing
- Hoyoung Chang, Soojin Kim, Seonyoung Lee, Kyeongsoon Cho:
High-performance architecture of H.264 integer-pixel motion estimation IP for real-time 1080HD video CODEC. 419-422 - Michael Guarisco, Hassan Rabah
FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding. 423-426 - Norman Nolte, Sören Moch, Markus Kock, Peter Pirsch:
Memory efficient programmable processor for bitstream processing and entropy decoding of multiple-standard high-bitrate HDTV video bitstreams. 427-431 - Yongseok Jin, Hyuk-Jae Lee:
Pixel-Parallel SPIHT for frame memory compression. 432-435 - Sang-Jin Lee, Kyung-Chang Park, Yeon-Ho Kim, Yun-ki Hong, Younggap You, Kyoung-Rok Cho, Tae Won Cho, Kamran Eshraghian:
System-on-System (SoS) architecture for 3-D secure imaging. 436-439
Tutorials
- Christian Haubelt:
Designing multi-processor Systems-on-Chip. 443 - Liam M. Devlin:
Microwave IC design for broadband receivers. 444 - Kaushik Roy:
Design in the nano-scale Era: Low-power, reliability, and error resiliency. 445 - Karsten Einwich, Christoph Grimm, Martin Barnasconi, Alain Vachoux:
Introduction to the SystemC AMS DRAFT standard. 446
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