default search action
ISLPD 1995: Dana Point, California, USA
- Massoud Pedram, Robert W. Brodersen, Kurt Keutzer:
Proceedings of the 1995 International Symposium on Low Power Design 1995, Dana Point, California, USA, April 23-26, 1995. ACM 1995, ISBN 0-89791-744-8 - Walter Davis:
The CAD challenges of designing low power, high performance VLSI system. 1 - Kimiyoshi Usami, Mark Horowitz:
Clustered voltage scaling technique for low-power design. 3-8 - Salil Raje, Majid Sarrafzadeh:
Variable voltage scheduling. 9-14 - Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin:
Unifying carry-sum and signed-digital number representations for low power. 15-20 - Luca Benini, Giovanni De Micheli:
Transformation and synthesis of FSMs for low-power gated-clock implementation. 21-26 - Christos A. Papachristou, Mark Spining, Mehrdad Nourani:
A multiple clocking scheme for low power RTL design. 27-32 - José Monteiro, Srinivas Devadas:
Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs. 33-38 - Peter A. Beerel, Cheng-Ta Hsieh, Suhrid A. Wadekar:
Estimation of energy consumption in speed-independent control circuits. 39-44 - Uming Ko, Poras T. Balsara, Ashwini K. Nanda:
Energy optimization of multi-level processor cache architectures. 45-49 - Sven Wuytack, Francky Catthoor, Hugo De Man:
Transforming set data types to power optimal data structures. 51-56 - Ramesh Panwar, David A. Rennels:
Reducing the frequency of tag compares for low power I-cache design. 57-62 - Ching-Long Su, Alvin M. Despain:
Cache design trade-offs for power and performance optimization: a case study. 63-68 - Aurobindo Dasgupta, Ramesh Karri
:
Simultaneous scheduling and binding for power minimization during microarchitecture synthesis. 69-74 - Anthony Correale Jr.:
Overview of the power minimization techniques employed in the IBM PowerPC 4xx embedded controllers. 75-80 - Diana Marculescu
Information theoretic measures of energy consumption at register transfer level. 81-86 - Farid N. Najm:
Towards a high-level power estimation capability. 87-92 - Paul E. Landman, Jan M. Rabaey:
Activity-sensitive architectural power analysis for the control path. 93-98 - Enric Musoll, Jordi Cortadella
High-level synthesis techniques for reducing the activity of functional units. 99-104 - Charlie X. Huang, Bill Zhang, An-Chang Deng, Burkhard Swirski:
The design and implementation of PowerMill. 105-110 - Abelardo Pardo, R. Iris Bahar
CMOS dynamic power estimation based on collapsible current source transistor modeling. 111-116 - Christian Piguet, Jean-Marc Masgonty, Vincent von Kaenel, Thierry Schneider:
Logic design for low-voltage/low-power CMOS circuits. 117-122 - Michele Favalli, Luca Benini:
Analysis of glitch power dissipation in CMOS ICs. 123-128 - S. Turgis, Nadine Azémard, Daniel Auvergne:
Explicit evaluation of short circuit power dissipation for CMOS logic structures. 129-134 - Premal Buch, Shen Lin, Vijay Nagasamy, Ernest S. Kuh:
Techniques for fast circuit simulation applied to power estimation of CMOS circuits. 135-138 - Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
High-throughput and low-power DSP using clocked-CMOS circuitry. 139-144 - William A. Chren Jr.:
Low delay-power product CMOS design using one-hot residue coding. 145-150 - Rafael Fried, Reuven Holzer:
Low power and EMI, high frequency, crystal oscillator. 151-154 - M. Tachibana, S. Kurosawa, R. Nojima, Norman Kojima, Masaaki Yamada, Takashi Mitsuhashi, Nobuyuki Goto:
Power and area optimization by reorganizing CMOS complex gate circuits. 155-160 - Alexey Glebov, David T. Blaauw, Larry G. Jones:
Transistor reordering for low power CMOS gates using an SP-BDD representation. 161-166 - Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint. 167-172 - Vamshi Veeramachaneni, Akhilesh Tyagi, Suresh Rajgopal:
Re-encoding for low power state assignment of FSMs. 173-178 - Jae W. Chung, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Optimization of power dissipation and skew sensitivity in clock buffer synthesis. 179-184 - Kei-Yong Khoo, Alan N. Willson Jr.:
Charge recovery on a databus. 185-189 - Alan Kramer, John S. Denker, B. Flower, J. Moroney:
2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits. 191-196 - David J. Frank, Paul M. Solomon:
Electroid-oriented adiabatic switching circuits. 197-202 - Alan Kramer, Roberto Canegallo, Mauro Chinosi, D. Doise, Giovanni Gozzini, Pier Luigi Rolandi, Marco Sabatini, P. Zabberoni:
Ultra-low-power analog associative memory core using flash-EEPROM-based programmable capacitors. 203-208 - Phillip E. Allen, Benjamin J. Blalock, Gabriel A. Rincon:
Low voltage analog circuits using standard CMOS technology. 209-214 - Anthony M. Hill, Sung-Mo Kang:
Determining accuracy bounds for simulation-based switching activity estimation. 215-220 - Vivek Tiwari, Sharad Malik
Guarded evaluation: pushing power management to logic synthesis/design. 221-226 - Christopher K. Lennard, A. Richard Newton:
An estimation technique to guide low power resynthesis algorithms. 227-232
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-15 19:44 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: