Article

Free access

Activity-sensitive architectural power analysis for the control path

Authors:

Paul E. Landman,

Jan M. RabaeyAuthors Info & Claims

ISLPED '95: Proceedings of the 1995 international symposium on Low power design

Pages 93 - 98

https://doi.org/10.1145/224081.224098

Published: 23 April 1995 Publication History

PDF eReader

References

[1]

A. Deng, "Power Analysis for CMOS/BiCMOS Circuits," 1994 International Workshop on Low Power Design, Napa Valley, CA, pp. 3-8, April 1994.

Google Scholar

[2]

P. Landman and J. Rabaey, "Black-Box Capacitance Models for Architectural Power Analysis," 1994 International Workshop on Low Power Design, pp. 165-170, April 1994.

Google Scholar

[3]

P. Landman and J. Rabaey, "Architectural Power Analysis: The Dual Bit Type Method," accepted to Transactions on VLSI Systems, June 1995.

Digital Library

Google Scholar

[4]

F. Najm, "A Survey of Power Estimation Techniques in VLSI Circuits," Transactions on VLSI Systems, vol. 2, no. 4, pp. 446-455, Dec. 1994.

Digital Library

Google Scholar

[5]

K. M~ller-Glaser, K. Kirsch, and K. Neusinger, "Estimating Essential Design Characteristics to Support Project Planning for ASIC Design Management," IEEE International Conference on Computer-Aided Design '91, pp. 148-151, Nov. 1991.

Google Scholar

[6]

C. Svensson and D. Liu, "A Power Estimation Tool and Prospects of Power Savings in CMOS VLSI Chips," 1994 International Workshop on Low-Power Design,p. 171-176, Apr. 1994.

Google Scholar

[7]

A. Salz and M. Horowitz, "IRSIM: An Incremental MOS Switch-Level Simulator," Proceedings of the 26th Design Automation Conference, pp. 173-178, 1989.

Digital Library

Google Scholar

[8]

R. Brayton, G. Hachtel, C. McMullen, and A. Sangiovanni- Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, 1984.

Digital Library

Google Scholar

[9]

R. W. Brodersen ed., Anatomy of a Silicon Compiler, Kluwer Academic Publishers, 1992.

Digital Library

Google Scholar

[10]

E Landman, Low-Power Architectural Design Methodologies, Ph.D. Dissertation, UC Berkeley, August 1994.

Digital Library

Google Scholar

Cited By

View all

Ibrahim MRupp MFahmy H(2011)A precise high-level power consumption model for embedded systems softwareEURASIP Journal on Embedded Systems10.1155/2011/4808052011(1-14)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1155/2011/480805
Pedram M(2009)Power Simulation and Estimation in VLSI CircuitsDesign Automation, Languages, and Simulations10.1201/9780203009284.ch11(11-1-11-27)Online publication date: 6-Nov-2009
https://doi.org/10.1201/9780203009284.ch11
Macii EPedram MSomenzi F(2006)High-level power modeling, estimation, and optimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.73618117:11(1061-1079)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.736181
Show More Cited By

Index Terms

Activity-sensitive architectural power analysis for the control path
1. Hardware

Recommendations

Power sensitive power control in ad networks
ACMSE '05 vol 2: Proceedings of the 43rd annual ACM Southeast Conference - Volume 2

In this paper, we propose battery power sensitive power control as a variable-range transmission power control strategy to maximize network lifetime and minimize end-to-end delay in wireless multi-hop networks. The network lifetime is defined as the time ...
Power aware routing using power control in Ad Hoc networks

A conventional routing protocol selects a path using the shortest number of hops as a routing metric. Is has been proposed that a different routing metric may be useful to achieve energy savings. One such power-aware routing metric is minimizing the ...
Activity-sensitive architectural power analysis

Prompted by demands for portability and low-cost packaging, the electronics industry has begun to view power consumption as a critical design criterion. As such there is a growing need for tools that can accurately predict power consumption early in the ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

ISLPED '95: Proceedings of the 1995 international symposium on Low power design

April 1995

233 pages

ISBN:0897917448

DOI:10.1145/224081

Chairmen:
Massoud Pedram
USC, Los Angeles, CA
,
Robert Brodersen
UCB, Berkeley, CA
,
Kurt Keutzer
Synopsys, Mountain View, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 April 1995

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

LPD95

Sponsor:

SIGDA
IEEE-CAS

LPD95: Low Power Design Symposium

April 23 - 26, 1995

California, Dana Point, USA

Acceptance Rates

Overall Acceptance Rate 398 of 1,159 submissions, 34%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

32
Total Citations
View Citations
424
Total Downloads

Downloads (Last 12 months)40
Downloads (Last 6 weeks)15

Reflects downloads up to 14 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Ibrahim MRupp MFahmy H(2011)A precise high-level power consumption model for embedded systems softwareEURASIP Journal on Embedded Systems10.1155/2011/4808052011(1-14)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1155/2011/480805
Pedram M(2009)Power Simulation and Estimation in VLSI CircuitsDesign Automation, Languages, and Simulations10.1201/9780203009284.ch11(11-1-11-27)Online publication date: 6-Nov-2009
https://doi.org/10.1201/9780203009284.ch11
Macii EPedram MSomenzi F(2006)High-level power modeling, estimation, and optimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.73618117:11(1061-1079)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.736181
Benini LDe Micheli G(2006)Automatic synthesis of low-power gated-clock finite-state machinesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.50393315:6(630-643)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.503933
Raghunathan ADey SJha N(2003)High-level macro-modeling and estimation techniques for switching activity and power consumptionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81229511:4(538-557)Online publication date: 1-Aug-2003
https://dl.acm.org/doi/10.1109/TVLSI.2003.812295
Chen RIrwin MBajwa R(2001)Architecture-level power estimation and design experimentsACM Transactions on Design Automation of Electronic Systems10.1145/371254.3712626:1(50-66)Online publication date: 1-Jan-2001
https://dl.acm.org/doi/10.1145/371254.371262
Carletta JPapachristou CNourani MBolsens I(2000)Detecting undetectable controller faults using power analysisProceedings of the conference on Design, automation and test in Europe10.1145/343647.344097(723-728)Online publication date: 1-Jan-2000
https://dl.acm.org/doi/10.1145/343647.344097
Carletta JPapachristou CNourani M(2000)Detecting undetectable controller faults using power analysisProceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537)10.1109/DATE.2000.840867(723-728)Online publication date: 2000
https://doi.org/10.1109/DATE.2000.840867
Marculescu DMarculescu RPedram MChandrakasan AKiaei S(1998)Theoretical bounds for switching activity analysis in finite-state machinesProceedings of the 1998 international symposium on Low power electronics and design10.1145/280756.280766(36-41)Online publication date: 10-Aug-1998
https://dl.acm.org/doi/10.1145/280756.280766
Chen ROwens RIrwin MBajwa RBajwa RChawla BBryant RRabaey J(1998)Validation of an architectural level power analysis techniqueProceedings of the 35th annual Design Automation Conference10.1145/277044.277106(242-245)Online publication date: 1-May-1998
https://dl.acm.org/doi/10.1145/277044.277106
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Power sensitive power control in ad networks

Power aware routing using power control in Ad Hoc networks

Activity-sensitive architectural power analysis