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ICICDT 2015: Leuven, Belgium
- 2015 International Conference on IC Design & Technology, ICICDT 2015, Leuven, Belgium, June 1-3, 2015. IEEE 2015, ISBN 978-1-4799-7669-0
- Yuichiro Mitani, Kazuya Matsuzawa:
Simple technique for prediction of breakdown voltage of ultrathin gate insulator under ESD testing. 1-4 - Moonju Cho, Alessio Spessot, Ben Kaczer, Marc Aoulaiche, Romain Ritzenthaler, Tom Schram, Pierre Fazan, Naoto Horiguchi, Dimitri Linten:
Off-state stress degradation mechanism on advanced p-MOSFETs. 1-4 - Nicolas André, Guoli Li, Pierre Gérard, Olivier Poncelet, Yun Zeng, Syed Zeeshan Ali, Florin Udrea, Laurent A. Francis, Denis Flandre
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Wide band study of silicon-on-insulator photodiodes on suspended micro-hotplates platforms. 1-4 - Wataru Mizubayashi, Takahiro Mori, Koichi Fukuda, Yongxun Liu, Takashi Matsukawa, Yuki Ishikawa, Kazuhiko Endo
PBTI for N-type tunnel FinFETs. 1-4 - Yukimasa Okada, Koji Eriguchi, Kouichi Ono:
Surface orientation dependence of ion bombardment damage during plasma processing. 1-5 - Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Simple wafer stacking 3D-FPGA architecture. 1-4 - Philip X.-L. Feng:
NEMS switches: Opportunities and challenges in emerging IC technologies. 1-6 - Thuy Dao, Mu-Ling Ger, Jiangkai Zuo:
Characterization of onset tunneling voltage (Vonset) walkout in high-voltage deep trench isolation on SOI. 1-4 - Taro Ikeda, Akira Tanihara, Nobuhiko Yamamoto, Shigeru Kasai, Koji Eriguchi, Kouichi Ono:
Plasma-induced photon irradiation damage on low-k dielectrics enhanced by Cu-line layout. 1-4 - Hua Fan, Kehong Liu, Airong Liu, Lishan Lv, Zhiliang Qiao, Qiang Li:
Overview of methods to increase linearity of high-performance ADC. 1-4 - Athanasios Kiouseloglou, Gabriele Navarro
Current pulse generator for multilevel cell programming of innovative PCM. 1-4 - Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu
Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices. 1-4 - Anuj Grover
Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs. 1-4 - Pieter Weckx, Ben Kaczer, Philippe J. Roussel, Francky Catthoor, Guido Groeseneken
Impact of time-dependent variability on the yield and performance of 6T SRAM cells in an advanced HK/MG technology. 1-4 - Bogdan Govoreanu, Leqi Zhang, Malgorzata Jurczak:
Selectors for high density crosspoint memory arrays: Design considerations, device implementations and some challenges ahead. 1-4 - Odysseas Zografos, Praveen Raghavan, Yasser Sherazi, Adrien Vaysset, Florin Ciubotaru
Area and routing efficiency of SWD circuits compared to advanced CMOS. 1-4 - Mirko Scholz, Shih-Hung Chen, Geert Hellings, Dimitri Linten, Roman Boschke:
Impact of local interconnects on ESD design. 1-4 - Herman Oprins, Vladimir Cherman, Geert Van der Plas, F. L. T. Maggioni, Joeri De Vos, Eric Beyne
Thermal experimental and modeling analysis of high power 3D packages. 1-4 - Azusa Oshima, Pieter Weckx, Ben Kaczer, Kazutoshi Kobayashi, Takashi Matsumoto:
Impact of random telegraph noise on ring oscillators evaluated by circuit-level simulations. 1-4 - Romain Ritzenthaler, Tom Schram, Geert Eneman, Anda Mocuta, Naoto Horiguchi, Aaron Voon-Yew Thean, Alessio Spessot, Marc Aoulaiche, Pierre Fazan, K. B. Noh, Y. Son:
Assessment of SiGe quantum well transistors for DRAM peripheral applications. 1-4 - Kazuyuki Tomida, Keizo Hiraga, Morin Dehan, Geert Hellings, Doyoung Jang, Kenichi Miyaguchi, Thomas Chiarella, Minsoo Kim, Anda Mocuta, Naoto Horiguchi, Abdelkarim Mercha, Diederik Verkest, Aaron Thean:
Impact of fin shape variability on device performance towards 10nm node. 1-4 - Roman Boschke, Guido Groeseneken
ESD protection diodes in optical interposer technology. 1-4 - M. Akbal, G. Ribes, M. Guillermet, L. Vallier:
Plasma induced damage investigation in the fully depleted SOI technology. 1-4 - Olivier Weber, Emmanuel Josse, J. Mazurier, Michel Haond:
Static and dynamic power management in 14nm FDSOI technology. 1-4 - Shengcheng Wang, Farshad Firouzi, Fabian Oboril, Mehdi Baradaran Tahoori:
Deadspace-aware Power/Ground TSV planning in 3D floorplanning. 1-4 - Mohammed Aqeeli, Abdullah Alburaikan, Xianjun Huang, Zhirun Hu:
Low-phase noise variation VCO implementing resistorless digitally controlled varactor. 1-4 - Ionut Radu
3D monolithic integration: Stacking technology and applications. 1-3 - Wim Schoenmaker, Philippe Galy:
Integrated front-end/back-end simulation of electromagnetic fields, Lorentz force effects and fast current surges in microelectronic protection devices. 1-4 - Romain Ritzenthaler, Tom Schram, M. J. Cho, Anda Mocuta, Naoto Horiguchi, Aaron Voon-Yew Thean, Alessio Spessot, Christian Caillat, Marc Aoulaiche, Pierre Fazan, K. B. Noh, Y. Son:
I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration. 1-4 - Nathalie Fievet, Praveen Raghavan, Rogier Baert, Frédéric Robert, Abdelkarim Mercha, Diederik Verkest, Aaron Thean:
Impact of device and interconnect process variability on clock distribution. 1-4 - Gaudenzio Meneghesso, Matteo Meneghini
Trapping induced parasitic effects in GaN-HEMT for power switching applications. 1-4 - Alessio Spessot, Romain Ritzenthaler, Tom Schram, Marc Aoulaiche, Moonju Cho, Maria Toledano-Luque, Naoto Horiguchi, Pierre Fazan:
Reliability impact of advanced doping techniques for DRAM peripheral MOSFETs. 1-4 - M. Ali Pourghaderi, Anda Mocuta, Aaron Thean:
Nonparabolicity and confinement effects of IIIV materials in novel transistors. 1-3 - Annachiara Spagnolo, Bob Verbruggen, Stefano D'Amico, Piet Wambacq:
High-speed analog-to-digital converters in downscaled CMOS. 1-4 - Chua-Chin Wang, Tsung-Yi Tsai, Wei Lin:
A high-speed 2×VDD output buffer with PVTL detection using 40-nm CMOS technology. 1-4 - Trong Huynh Bao
Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM. 1-4 - S. Athanasiou
Preliminary 3D TCAD electro-thermal simulations of BIMOS transistor in thin silicon film for ESD protection in FDSOI UTBB CMOS technology. 1-4 - Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger:
Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA. 1-4 - Geert Eneman, An De Keersgieter, Anda Mocuta, Nadine Collaert
FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below. 1-4 - Kenichi Miyaguchi, Bertrand Parvais, Lars-Åke Ragnarsson, Piet Wambacq, Praveen Raghavan, Abdelkarim Mercha, Anda Mocuta, Diederik Verkest, Aaron Thean:
Modeling FinFET metal gate stack resistance for 14nm node and beyond. 1-4 - A. Rouhi Najaf Abadi, W. Guo, X. Sun, K. Ben Ali, Jean-Pierre Raskin, Martin Rack, C. Roda Neve, M. Choi, V. Moroz, Geert Van der Plas, Ingrid De Wolf, Eric Beyne
Through silicon via to FinFET noise coupling in 3-D integrated circuits. 1-4 - Dmitry Yakimets, Doyoung Jang, Praveen Raghavan, Geert Eneman, Hans Mertens, P. Schuddinck, Arindam Mallik, Marie Garcia Bardon, Nadine Collaert, Abdelkarim Mercha, Diederik Verkest, Aaron Thean, Kristin De Meyer:
Lateral NWFET optimization for beyond 7nm nodes. 1-4 - Marie Garcia Bardon, P. Schuddinck, Praveen Raghavan, Doyoung Jang, Dmitry Yakimets, Abdelkarim Mercha, Diederik Verkest, Aaron Thean:
Dimensioning for power and performance under 10nm: The limits of FinFETs scaling. 1-4 - Ronald P. Luijten, Matteo Cossale, Rolf Clauberg
Power measurements and cooling of the DOME 28nm 1.8GHz 24-thread ppc64 μServer compute node. 1-4 - Ashish Kumar, Vinay Kumar, Dhori Kedar Janardan, G. S. Visweswaran, Kaushik Saha:
A 6T-SRAM in 28nm FDSOI technology with Vmin of 0.52V using assisted read and write operation. 1-4 - Duc-Hung Le
Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB process. 1-4 - Yoshitaka Yamauchi
Optimal design to maximize efficiency of single-inductor multiple-output buck converters in discontinuous conduction mode for IoT applications. 1-4 - Jan Ackaert, Tony Colpaert, Aditi Malik, Mario Gonzalez:
Metallization scheme optimization of plastic-encapsulated electronic power devices. 1-4
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