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ITC 2017: Fort Worth, TX
- IEEE International Test Conference, ITC 2017, Fort Worth, TX, USA, October 31 - Nov. 2, 2017. IEEE 2017, ISBN 978-1-5386-3413-4
- Bob Klosterboer:
Testing beyond the green light. 1 - Sanu Mathew:
Security keynote: Ultra-low-energy security circuit primitives for IoT platforms. 1 - Joachim Kunkel:
Automotive keynote: Look Mom! No hands! 1 - Nimit Jain, Nitin Agarwal, Rajavelu Thinakaran, Rubin A. Parekhji:
Low cost dynamic error detection in linearity testing of SAR ADCs. 1-8 - Sabyasachi Deyati, Barry J. Muldrey, Byunghoo Jung, Abhijit Chatterjee:
Concurrent built in test and tuning of beamforming MIMO systems using learning assisted performance optimization. 1-10 - Xiankun Jin, Tao Chen
, Mayank Jain, Arun Kumar Barman, David Kramer, Doug Garrity, Randall L. Geiger, Degang Chen:
An on-chip ADC BIST solution and the BIST enabled calibration scheme. 1-10 - Jae Woong Jeong, Ender Yilmaz, LeRoy Winemberg, Sule Ozev:
Built-in self-test for stability measurement of low dropout regulator. 1-9 - Saurabh Gupta, Al Crouch, Jennifer Dworak, Daniel Engels:
Increasing IJTAG bandwidth and managing security through parallel locking-SIBs. 1-10 - Krishna Chakravadhanula, Vivek Chickermane, Paul Cunningham, Brian Foutz, Dale Meehl, Louis Milano, Christos Papameletis, David Scott, Steev Wilcox:
Advancing test compression to the physical dimension. 1-10 - Sylwester Milewski, Nilanjan Mukherjee, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada:
Full-scan LBIST with capture-per-cycle hybrid test points. 1-9 - Ying Zhang, Krishnendu Chakrabarty
Software-based online self-testing of network-on-chip using bounded model checking. 1-10 - Sonal Pinto, Michael S. Hsiao:
RTL functional test generation using factored concolic execution. 1-10 - Christopher J. Lukas
Modeling trans-threshold correlations for reducing functional test time in ultra-low power systems. 1-10 - Constantinos Xanthopoulos, Peter Sarson, Heinz Reiter, Yiorgos Makris
Automated die inking: A pattern recognition-based approach. 1-6 - Zeye Liu, Phillip Fynan, Ronald D. Blanton:
Front-end layout reflection for test chip design. 1-10 - Souhir Mhira, Vincent Huard, Ahmed Benhassain, Florian Cacho, David Meyer, Sylvie Naudet, Abhishek Jain, C. R. Parthasarathy, Alain Bravaix
Cognitive approach to support dynamic aging compensation. 1-7 - Shi Jin, Zhaobo Zhang, Krishnendu Chakrabarty
Changepoint-based anomaly detection in a core router system. 1-10 - Shi Jin, Zhaobo Zhang, Krishnendu Chakrabarty
Symbol-based health-status analysis in a core router system. 1-10 - V. Prasanth
Safety analysis for integrated circuits in the context of hybrid systems. 1-10 - Tal Kogan, Yehonatan Abotbol, Gabriele Boschi, Gurgen Harutyunyan, I. Kroul, Hanna Shaheen, Yervant Zorian:
Advanced functional safety mechanisms for embedded memories and IPs in automotive SoCs. 1-6 - Li-C. Wang, Sebastian Siatkowski, Chuanhe Jay Shan, Matthew Nero, Nikolas Sumikawa, LeRoy Winemberg:
Some considerations on choosing an outlier method for automotive product lines. 1-10 - Subhadip Kundu, Kuldip Kumar, Rishi Kumar, Rohit Kapur:
Diagnosing multiple faulty chains with low pin convolution compressor using compressed production test set. 1-7 - Srikanth Venkataraman, Irith Pomeranz, Shraddha Bodhe, M. Enamul Amyeen:
Test reordering for improved scan chain diagnosis using an enhanced defect diagnosis procedure. 1-9 - Chuanhe Jay Shan, Pietro Babighian, Yan Pan, John M. Carulli, Li-C. Wang:
Systematic defect detection methodology for volume diagnosis: A data mining perspective. 1-10 - Sameer Chillarige, Anil Malik, Sharjinder Singh, Joe Swenton, Krishna Chakravadhanula:
High throughput multiple device diagnosis system. 1-10 - W. Pradeep, P. Narayanan, R. Mittal, N. Maheshwari, N. Naresh:
Frequency scaled segmented (FSS) scan architecture for optimized scan-shift power and faster test application time. 1-10 - Yan Dong, Grady Giles, GuoLiang Li, Jeff Rearick, John Schulze, James Wingfield, Tim Wood:
Maximizing scan pin and bandwidth utilization with a scan routing fabric. 1-10 - Xijiang Lin:
On applying scan based structural test for designs with dual-edge triggered flip-flops. 1-8 - Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen:
Analysis and mitigation or IR-Drop induced scan shift-errors. 1-8 - Baris Esen, Anthony Coyette, Nektar Xama, Wim Dobbelaere, Ronny Vanhooren, Georges G. E. Gielen:
Non-intrusive detection of defects in mixed-signal integrated circuits using light activation. 1-7 - Li Xu, Yuming Zhuang
Accurate ADC testing with significantly relaxed instrumentation including large cumulative jitter. 1-10 - Masahiro Ishida, Kiyotaka Ichiyama:
A jitter separation and BER estimation method for asymmetric total jitter distributions. 1-9 - Arani Sinha, Sujay Pandey, Ayush Singhal, Alodeep Sanyal, Alan Schmaltz:
DFM-aware fault model and ATPG for intra-cell and inter-cell defects. 1-10 - Masayuki Arai, Shingo Inuyama, Kazuhiko Iwasaki:
Layout-aware 2-step window-based pattern reordering for fast bridge/open test generation. 1-8 - Irith Pomeranz:
Selecting target bridging faults for uniform circuit coverage. 1-7 - Adib Nahiyan, Mehdi Sadi, Rahul Vittal, Gustavo K. Contreras, Domenic Forte
Hardware trojan detection through information flow security verification. 1-10 - Rana Elnaggar, Krishnendu Chakrabarty
Run-time hardware trojan detection using performance counters. 1-10 - Jiafan Wang, Congyin Shi, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu:
Thwarting analog IC piracy via combinational locking. 1-10 - Xiaoan Ding, Xi Liang, Yanjing Li:
Cross-layer refresh mitigation for efficient and reliable DRAM systems: A comparative study. 1-10 - Valentin Gherman, Emna Farjallah, Jean-Marc Armani, Marcelino Seif, Luigi Dilillo:
Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with the help of embedded statistics. 1-9 - Raphael Robertazzi, Micheal Scheurman, Matt Wordeman, Shurong Tian, Christy Tyberg:
Analytical test of 3D integrated circuits. 1-10 - Peter Sarson, Jeff Rearick:
Use models for extending IEEE 1687 to analog test. 1-8 - Michael Laisne, Hans Martin von Staudt, Sourabh Bhalerao, Mark Eason:
Single-pin test control for Big A, little D devices. 1-10 - Sergei Odintsov
Marginal PCB assembly defect detection on DDR3/4 memory bus. 1-10 - Nik Sumikawa, Matt Nero, Li-C. Wang:
Kernel based clustering for quality improvement and excursion detection. 1-10 - Ankush Srivastava, Adit D. Singh, Virendra Singh, Kewal K. Saluja:
Exploiting path delay test generation to develop better TDF tests for small delay defects. 1-10 - Irith Pomeranz:
POSTT: Path-oriented static test compaction for transition faults in scan circuits. 1-8 - V. Prasanth
Demystifying automotive safety and security for semiconductor developer. 1-10 - Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian:
An effective functional safety solution for automotive systems-on-chip. 1-10 - Bing-Yang Lin, Hsin-Wei Hung, Shu-Mei Tseng, Chi Chen, Cheng-Wen Wu
Highly reliable and low-cost symbiotic IOT devices and systems. 1-10 - Shuo-Lian Hong, Kuen-Jong Lee:
A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems. 1-10 - Matthew Beckler
Fault simulation acceleration for TRAX dictionary construction using GPUs. 1-9 - Stephen Sunter, Peter Sarson:
A/MS benchmark circuits for comparing fault simulation, DFT, and test generation methods. 1-7 - Boyang Du, Luca Sterpone
Fault tolerant electronic system design. 1-6 - Yuming Zhuang
Accurate and robust spectral testing with relaxed instrumentation requirements. 1-10 - Surajit Kumar Roy, Chandan Giri
Design-for-test and test time optimization for 3D SOCs. 1-10
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