default search action
DFT 2005: Monterey, CA, USA
- 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA. IEEE Computer Society 2005, ISBN 0-7695-2464-8
Cover
- Title Page.
- Copyright.
Introduction
- Message from the Symposium Chairs.
- Committees.
Yield Analysis and Modeling
- Mehdi Baradaran Tahoori:
Defects, Yield, and Design in Sublithographic Nano-electronics. 3-11 - Zhaojun Wo, Israel Koren, Maciej J. Ciesielski:
An ILP Formulation for Yield-driven Architectural Synthesis. 12-20 - Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone:
Design and Analysis of Self-Repairable MEMS Accelerometer. 21-32
Scan Design and Test Data Compression
- Jinkyu Lee, Nur A. Touba:
Low Power BIST Based on Scan Partitioning. 33-41 - Samuel I. Ward, Chris Schattauer, Nur A. Touba:
Using Statistical Transformations to Improve Compression for Linear Decompressors. 42-50 - Jeremy Lee, Mohammad Tehranipoor, Chintan Patel, Jim Plusquellic:
Securing Scan Design Using Lock and Key Technique. 51-62
Reconfiguration
- Masaru Fukushi, Yusuke Fukushima, Susumu Horiguchi:
A Genetic Approach for the Reconfiguration of Degradable Processor Arrays. 63-71 - Luca Breveglieri, Israel Koren, Paolo Maistri:
Incorporating Error Detection and Online Reconfiguration into a Regular Architecture for the Advanced Encryption Standard. 72-80 - Chin-Lung Su, Yi-Ting Yeh, Cheng-Wen Wu:
An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement. 81-92
Error Correcting Codes and Circuits
- Haruhiko Kaneko:
Error Control Coding for Semiconductor Memory Systems in the Space Radiation Environment. 93-101 - Siavash Bayat Sarmadi, M. Anwar Hasan:
Concurrent Error Detection of Polynomial Basis Multiplication over Extension Fields using a Multiple-bit Parity Scheme. 102-110 - Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano:
A Self Checking Reed Solomon Encoder: Design and Analysis. 111-119 - Jien-Chung Lo, Yu-Lun Wan, Eiji Fujiwara:
Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes. 120-130
Fault Detection and Tolerance for Sensor and Flash Memory
- B. Saillet, Jean-Michel Portal, Didier Née:
Flash Memory Cell: Parametric Test Data Reconstruction for Process Monitoring. 131-139 - Cory Jung, Mohammad Hadi Izadi, Michelle L. La Haye:
Noise Analysis of Fault Tolerant Active Pixel Sensors. 140-148 - Glenn H. Chapman, Israel Koren, Zahava Koren, Jozsef Dudas, Cory Jung:
On-Line Identification of Faults in Fault-Tolerant Imagers. 149-157 - Glenn H. Chapman, Vijay K. Jain, Shekhar Bhansali
:
Inter-Plane Via Defect Detection Using the Sensor Plane in 3-D Heterogeneous Sensor Systems. 158-168
Delay Fault Test and Timing Consideration
- Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak:
The Other Side of the Timing Equation: a Result of Clock Faults. 169-177 - Lei Wu, D. M. H. Walker:
A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits. 178-186 - Nisar Ahmed, Mohammad Tehranipoor:
Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique. 187-198
Defect and Fault Tolerant Design in QCA Circuits
- Mariam Momenzadeh, Jing Huang, Fabrizio Lombardi:
Defect Characterization and Tolerance of QCA Sequential Devices and Circuits. 199-207 - Mariam Momenzadeh, Marco Ottavi
Modeling QCA Defects at Molecular-level in Combinational Circuits. 208-216 - Zachary D. Patitz, Nohpill Park, Minsu Choi, Fred J. Meyer:
QCA-Based Majority Gate Design under Radius of Effect-Induced Faults. 217-228
Interconnect Test
- David M. Horan, Richard A. Guinee:
A Novel Pulse Echo Correlation Tool for Transmission Path Testing and Fault Finding using Pseudorandom Binary Sequences. 229-237 - Cristian Grecu, Partha Pratim Pande, Baosheng Wang, André Ivanov, Res Saleh:
Methodologies and Algorithms for Testing Switch-Based NoC Interconnects. 238-246 - Roberto Gómez, Alejandro Girón, Víctor H. Champac:
Test of Interconnection Opens Considering Coupling Signals. 247-258
Case Studies and Applications
- Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano:
FPGA oriented design of parity sharing RS codecs. 259-265 - Mahdi Fazeli, Reza Farivar, Seyed Ghassem Miremadi:
A Software-Based Concurrent Error Detection Technique for PowerPC Processor-based Embedded Systems. 266-274 - G. Cellere, Alessandro Paccagnella, Angelo Visconti, Mauro Bonanomi:
Soft Errors induced by single heavy ions in Floating Gate memory arrays. 275-284 - Kyung Ki Kim, Jing Huang, Yong-Bin Kim, Fabrizio Lombardi:
On the Modeling and Analysis of Jitter in ATE Using Matlab. 285-293 - Kyung Ki Kim, Yong-Bin Kim, Fabrizio Lombardi:
Data Dependent Jitter (DDJ) Characterization Methodology. 294-304
Interactive Session
- Mohammad Tehranipoor:
Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure. 305-313 - Erik Schüler, Luigi Carro:
Reliable Digital Circuits Design using Sigma-Delta Modulated Signals. 314-324 - Dilip P. Vasudevan, Parag K. Lala:
A Technique for Modular Design of Self-Checking Carry-Select Adder. 325-333 - Cristiana Bolchini, Antonio Miele, Fabio Salice, Donatella Sciuto:
A model of soft error effects in generic IP processors. 334-342 - Vladimir Ostrovsky, Ilya Levin:
Implementation of Concurrent Checking Circuits by Independent Sub-circuits. 343-351 - Daniele Rossi, Martin Omaña, Fabio Toma, Cecilia Metra:
Multiple Transient Faults in Logic: An Issue for Next Generation ICs. 352-360 - Fang Yu, Chung-Hung Tsai, Yao-Wen Huang, D. T. Lee, Hung-Yau Lin, Sy-Yen Kuo:
Efficient Exact Spare Allocation via Boolean Satisfiability. 361-370 - Jia Di, Parag K. Lala, Dilip P. Vasudevan:
On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits. 371-379 - Bhushan Vaidya, Mehdi Baradaran Tahoori:
Delay Test Generation with All Reachable Output Propagation and Multiple Excitations. 380-388 - Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi:
Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment. 389-397 - Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz:
On Generating Pseudo-Functional Delay Fault Tests for Scan Designs. 398-405 - Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda:
Should Illinois-Scan Based Architectures be Centralized or Distributed? 406-414 - Leonard Lee, Sean H. Wu, Charles H.-P. Wen, Li-C. Wang:
On Generating Tests to Cover Diverse Worst-Case Timing Corners. 415-426
Approaches for Soft Error
- Wei Zhang:
Computing Cache Vulnerability to Transient Errors and Its Implication. 427-435 - Luca Sterpone, Massimo Violante:
A design flow for protecting FPGA-based systems against single event upsets. 436-444 - Paolo Bernardi, Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda
An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors. 445-453 - Jeetendra Kumar, Mehdi Baradaran Tahoori:
A Low Power Soft Error Suppression Technique for Dynamic Logic. 454-462 - Hossein Asadi, Mehdi Baradaran Tahoori:
Soft Error Modeling and Protection for Sequential Elements. 463-474
On-line and Concurrent Fault Detection
- Irith Pomeranz, Sudhakar M. Reddy:
Recovery During Concurrent On-Line Testing of Identical Circuits. 475-483 - Song Peng, Rajit Manohar:
Efficient Failure Detection in Pipelined Asynchronous Circuits. 484-493 - Ernesto Sánchez, Matteo Sonza Reorda
On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors. 494-504
Fault and Error Tolerant Systems
- Masato Kitakami, Manabu Sueishi:
Fault-Tolerant Wormhole Switching with Backtracking Capability. 505-513 - Hyukjune Chung, Antonio Ortega:
Analysis and Testing for Error Tolerant Motion Estimation. 514-522 - In Suk Chong, Antonio Ortega:
Hardware Testing For Error Tolerant Multimedia Compression based on Linear Transforms. 523-534
Test Scheduling and Software-based Test
- Miltiadis Hatzimihail, Mihalis Psarakis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis:
Software-Based Self-Test for Pipelined Processors: A Case Study. 535-543 - Enkelejda Tafaj, Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty:
Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling. 544-551 - Chunsheng Liu, Kugesh Veeraraghavant, Vikram Iyengar:
Thermal-Aware Test Scheduling and Hot Spot Temperature Minimization for Core-Based Systems. 552-562
Testing and Design for Analog Circuits
- Shaolei Quan, Meng-Yao Liu, Chin-Long Wey:
Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress. 563-572 - Yukiya Miura:
Characteristics of Fault Diagnosis for Analog Circuits Based on Preset Test. 573-581 - Michael Wieckowski, John C. Liobe, Quentin Diduck, Martin Margala:
A New Test Methodology For DNL Error In Flash ADC's. 582-590 - Sadeka Ali, Gregory Briggs, Martin Margala:
A High Frequency, Low Jitter Auto-Calibration Phase-Locked Loop with Built-in-Self-Test. 591-600
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-15 19:43 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: