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A-SSCC 2015: Xia'men, China
- IEEE Asian Solid-State Circuits Conference, A-SSCC 2015, Xia'men, China, November 9-11, 2015. IEEE 2015, ISBN 978-1-4673-7191-9
- Hai Huang, Ling Du, Yun Chiu:
A 1.2-GS/s 8-bit two-step SAR ADC in 65-nm CMOS with passive residue transfer. 1-4 - Yutao Wang, Zhangming Zhu, Jiaojiao Yao, Yintang Yang:
A 0.45 V, 15.6 nW MOSFET-only sub-threshold voltage reference with no amplifiers. 1-4 - Hyeon-June Kim, Sun-Il Hwang, Ji-Wook Kwon, Dong-Hwan Jin, Byoung Soo Choi, Sang-Gwon Lee, Jong-Ho Park, Jang-Kyoo Shin, Seung-Tak Ryu:
Delta readout scheme for image-dependent power savings in a CMOS image sensor with multi-column-parallel SAR ADCs. 1-4 - Yang Zhao, Jian Zhao, Guo Ming Xia, An Ping Qiu, Yan Su, Xi Wang, Yong Ping Xu:
A 0.57°/h bias instability 0.067°/√h angle random walk MEMS gyroscope with CMOS readout circuit. 1-4 - Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A calibration-free time difference accumulator using two pulses propagating on a single buffer ring. 1-4 - Jingcheng Wang, Nathaniel Ross Pinckney, David T. Blaauw, Dennis Sylvester:
Reconfigurable self-timed regenerators for wide-range voltage scaled interconnect. 1-4 - Pai-Yi Wang, Szu-Yu Huang, Kuan-Yu Fang, Tai-Haur Kuo:
An undershoot/overshoot-suppressed current-mode buck converter with voltage-setting control for type-II compensator. 1-4 - Junfeng Jiang, Kofi A. A. Makinwa:
A multi-path CMOS Hall sensor with integrated ripple reduction loops. 1-4 - Fengwei An
, Keisuke Mihara, Shogo Yamazaki, Lei Chen, Hans Jürgen Mattausch:
Word-parallel associative memory for k-nearest-neighbor with configurable storage space of reference vectors. 1-4 - Yong Wang
A K-band pulse radar transceiver with highly digital closed-loop time-of-flight measurement. 1-4 - Kyoya Takano
124-GHz CMOS quadrature voltage-controlled oscillator with fundamental injection locking. 1-4 - Sungwook Choi, KyuTae Park, Marco Passerini, HeeJoung Park, DoYoung Kim, ChiHyun Kim, Kunwoo Park, Jinwoong Kim:
A cell current compensation scheme for 3D NAND FLASH memory. 1-4 - Huan-Sheng Chen, Hung-Yu Tsai, Li-Xuan Chuo, Yu-Kai Tsai, Liang-Hung Lu:
A 5.2-GHz full-integrated RF front-end by T/R switch, LNA, and PA co-design with 3.2-dB NF and +25.9-dBm output power. 1-4 - Matteo Ramella, Ivan Fabiano, Danilo Manstretta
A 1.7-2.1GHz +23dBm TX power compatible blocker tolerant FDD receiver with integrated duplexer in 28nm CMOS. 1-4 - Hyunki Kim, Kiseok Song, Taehwan Roh, Hoi-Jun Yoo:
A 95% accurate EEG-connectome processor for a mental health monitoring system. 1-4 - Masahiko Maruyama, Shigenari Taguchi, Masafumi Yamanoue, Kunihiko Iizuka:
A 24-bit multi-functional sensor analog front end employing low noise biasing technique with 8.2nV/√Hz input referred noise. 1-4 - Leo Li:
IC challenges in 5G. 1-4 - Jaehwa Kwak, Borivoje Nikolic
A 550-2260MHz self-adjustable clock generator in 28nm FDSOI. 1-4 - Chi-Huan Chiang, Chang-Cheng Huang, Shen-Iuan Liu:
A digital bang-bang phase-locked loop with bandwidth calibration. 1-4 - Tai-Chuan Ou, Zhengya Zhang
A 934MHz 9Gb/s 3.2pJ/b/iteration charge-recovery LDPC decoder with in-package inductors. 1-4 - Chen-Kai Hsu, Tai-Cheng Lee:
A single-channel 10-b 400-MS/s 8.7-mW pipeline ADC in a 90-nm technology. 1-4 - Hideki Shinohara, Kousuke Miyaji:
A ZVS CMOS active diode rectifier with voltage-time-conversion delay-locked loop for wireless power transmission. 1-4 - Lilan Yu, Masaya Miyahara, Akira Matsuzawa:
A 9-bit 1.8-GS/s pipelined ADC using linearized open-loop amplifiers. 1-4 - Daisaburo Takashima, Masato Endo, Kazuhiro Shimazaki, Manabu Sai, Masaaki Tanino:
A 7T-SRAM with data-write technique by capacitive coupling. 1-4 - Matteo Ramella, Ivan Fabiano, Danilo Manstretta
A 2.4GHz low-power SAW-less receiver for SoC coexistence. 1-4 - Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Noriaki Shirai, Shigeaki Kawai, Tomoyuki Arai, Yutaka Ide, Kazuhiro Terashima, Hirohito Higashi, Tomokazu Higuchi, Naoaki Naka:
A 28-Gb/s 4.5-pJ/bit transceiver with 1-tap decision feedback equalizer in 28-nm CMOS. 1-4 - Zhaoyang Weng, Shaoquan Gao, Jingjing Dong, Kai Yang, Hanjun Jiang, Fule Li, Zhihua Wang, Yanqing Ning, Xinkai Chen:
Dedicated ICs for wearable body sound monitoring. 1-4 - Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka
A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking. 1-4 - Guansheng Li, Wooram Lee, Delong Cui, Bo Zhang, Afshin Momtaz, Jun Cao:
Standing wave based clock distribution technique with application to a 10 × 11 Gbps transceiver in 28 nm CMOS. 1-4 - Ni Xu, Yiyu Shen, Sitao Lv, Woogeun Rhee
A spread-spectrum clock generator with FIR-embedded binary phase detection and 1-bit high-order ΔΣ modulation. 1-4 - Jan A. Angevare, Lorenzo Pedala, Ugur Sonmez, Fabio Sebastiano
A 2800-μm2 thermal-diffusivity temperature sensor with VCO-based readout in 160-nm CMOS. 1-4 - Y. J. Du, W. Su, S. Tolunay, L. Zhang, M. Kaynak, R. Scholz, Yong-Zhong Xiong:
220GHz wide-band MEMS switch in standard BiCMOS technology. 1-4 - Kok-Hin Teng, Tong Wu, Zhi Yang, Chun-Huat Heng, Xiayun Liu:
A 400-MHz wireless neural signal processing IC with 625× on-chip data reduction and reconfigurable BFSK/QPSK transmitter based on sequential injection locking. 1-4 - Sangyeun Cho:
Fast memory and storage architectures for the big data era. 1-4 - Zhao-yang Liu, Liyuan Liu, Jie Yang, Nanjian Wu:
A fully-integrated 860-GHz CMOS terahertz sensor. 1-4 - Qixian Shi, Davide Guermandi, Jan Craninckx
Flicker noise upconversion mechanisms in K-band CMOS VCOs. 1-4 - Yen-Ting Lin, Shin-Chi Lai, Shin-Hao Chen, Shen-Yu Peng, Ke-Horng Chen
99.4% peak audio signal recovery rate and ultra-low 0.32dB matching error with 10Hz high resolution filter fitting wearable aided speech compensation system. 1-4 - Athanasios Sarafianos, Joachim Pichler, Christoph Sandner, Michiel Steyaert
A folding dickson-based fully integrated wide input range capacitive DC-DC converter achieving Vout/2-resolution and 71% average efficiency. 1-4 - Joo-Hyung Chae
A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers. 1-4 - Yi-Chieh Huang, Che-Fu Liang, Ping-Ying Wang:
A 1V fractional-N PLL with nonlinearity-insensitive modulator. 1-4 - Dang Liu, Xiaofeng Liu, Woogeun Rhee
A 7.6mW 2Gb/s proximity transmitter for smartphone-mirrored display applications. 1-4 - Ronald Perez:
Silicon systems security and building a root of trust. 1-4 - Lei Yao, Peng Li, Minkyu Je:
A pulse-width-adaptive active charge balancing circuit with pulse-insertion based residual charge compensation and quantization for electrical stimulation applications. 1-4 - Babak Mohammadi, Joachim Neves Rodrigues:
Ultra low energy and area efficient charge pump with automatic clock controller in 65 nm CMOS. 1-4 - Tsun-Yuan Fan, Tsung-Yi Chou, Wen-Hua Chang:
A 0.11mm⁁2 150mW 10GBase-T transmitter in 28nm CMOS process. 1-4 - Marco Vigilante, Patrick Reynaert
A 25-102GHz 2.81-5.64mW tunable divide-by-4 in 28nm CMOS. 1-4 - Chia-Chi Kuo
A 132dB DR readout IC with pulse width modulation for IR focal plane arrays. 1-4 - Bertrand Parvais
A digital intensive circuit for low-frequency noise monitoring in 28nm CMOS. 1-4 - Matthew J. Turnquist, Markus Hiienkari, Jani Mäkipää, Lauri Koskinen:
A fully integrated self-oscillating switched-capacitor DC-DC converter for near-threshold loads. 1-4 - Allen Waters, Un-Ku Moon:
A fully automated verilog-to-layout synthesized ADC demonstrating 56dB-SNDR with 2MHz-BW. 1-4 - Xiaoyang Zhang, Zhe Zhang, Yongfu Li, Changrong Liu, Yongxin Guo
A 2.89-μW clockless wireless dry-electrode ECG SoC for wearable sensors. 1-4 - Meng Li, Jan-Willem Weijers, Veerle Derudder, Ilse Vos, Maxim Rykunov, Steven Dupont, Peter Debacker, Andy Dewilde, Yanxiang Huang, Liesbet Van der Perre
An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS. 1-5 - Wouter Steyaert, Patrick Reynaert
A THz signal source with integrated antenna for non-destructive testing in 28nm bulk CMOS. 1-4 - Zheng Song, Xiliang Liu, Zongming Jin, Xiaokun Zhao, Qiongbing Liu, Yun Yin, Baoyong Chi:
A 180nm CMOS wireless transceiver by utilizing guard band for narrowband IoT applications. 1-4 - Li-Yang Chen, Pen-Jui Peng
CW/FMCW/pulse radar engines for 24/26GHz multi-standard applications in 65nm CMOS. 1-4 - Chao Yuan, Kian Ann Ng, Yong Ping Xu, Shih-Cheng Yen, Nitish V. Thakor:
A 1-V 9.8-ENOB 100-kS/s single-ended SAR ADC with symmetrical DAC switching technique for neural signal acquisition. 1-4 - Chung-Yu Wu, Chia-Shiung Ho:
An 8-channel chopper-stabilized analog front-end amplifier for EEG acquisition in 65-nm CMOS. 1-4 - Injoon Hong, Seongwook Park, Junyoung Park, Hoi-Jun Yoo:
A 1.9nJ/pixel embedded deep neural network processor for high speed visual attention in a mobile vision recognition SoC. 1-4 - Shon-Hang Wen, Chien-Ming Chen, Cheng-Chung Yang, Chieh-Hung Chen, Jia-Feng Jiang, Keng-Jan Hsiao, Cheng-Yu Chien:
A 130dB PSRR, 108dB DR and 95dB SNDR, ground-referenced audio decoder with PSRR-enhanced load-adaptive Class-G 16Ohm headphone amplifiers. 1-4 - Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin
A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation. 1-4 - Jui-Che Su, Wei-Chung Chen, Wei-Tin Lin, Ying-Wei Chou, Meng-Wei Chien, Chin-Long Wey, Ke-Horng Chen
Pseudo AC current synthesizer and DC offset-corrected technique in constant-on-time control buck converter for werable electronics. 1-4 - Tomoya Ishii, Shogo Hachiya, Sheyang Ning, Masahiro Tanaka, Ken Takeuchi:
0.6 V operation, 26% smaller voltage ripple, 9% energy efficient boost converter with adaptively optimized comparator bias-current for ReRAM program in low power IoT embedded applications. 1-4 - Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae
A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm. 1-4 - Kelvin Yi-Tse Lai, Ming-Feng Shiu, Yi-Wen Lu, Yingchieh Ho, Yu-Chi Kao, Yu-Tao Yang, Gary Wang, Keng-Ming Liu, Hsie-Chia Chang, Chen-Yi Lee:
A field-programmable lab-on-a-chip with built-in self-test circuit and low-power sensor-fusion solution in 0.35μm standard CMOS process. 1-4 - Haikun Jia, Baoyong Chi, Lixue Kuang, Wei Zhu, Zhiping Wang, Feng Ma, Zhihua Wang:
A frequency doubling two-path phased-array FMCW radar transceiver in 65nm CMOS. 1-4 - Nicholas Preyss, Christian Senning, Andreas Burg
A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm. 1-4 - Yang You, Sudipto Chakraborty, Rui Wang, Jinghong Chen:
A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOS. 1-4 - Zhichao Tan, Mick Mueck, Xiao Hong Du, Larry Getzin, Michael Guidry, Flow Zhao, Baoxing Chen:
A fully isolated delta-sigma ADC for shunt based current sensing. 1-4 - Sung-Yong Kim, Xuefan Jin
A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy. 1-4 - Wei-Hsin Tseng, Wei-Liang Lee, Chang-Yang Huang, Pao-Cheng Chiu:
A 12-bit 104-MS/s SAR ADC in 28nm CMOS for digitally-assisted wireless transmitters. 1-4 - Sheng-Lyang Jang, Wen-Cheng Lai
A wide-band divide-by-3 injection-locked frequency divider using tunable MOS resistor. 1-5 - Burak Erbagci, Fangfei Liu, Cagla Cakir, Nail Etkin Can Akkaya, Ruby B. Lee, Ken Mai:
A 32kB secure cache memory with dynamic replacement mapping in 65nm bulk CMOS. 1-4 - Liang-Ting Kuo, Chun-Chih Hou, Meng-Hsuan Wu, Yun-Shiang Shu:
A 1V 9pA analog front end with compressed sensing for electrocardiogram monitoring. 1-4 - Jiacheng Wang, Wang Ling Goh, Xin Liu, Jun Zhou:
A 12.77-MHz on-chip relaxation oscillator with digital compensation for loop delay variation. 1-4 - Hideto Hidaka:
How future mobility meets IT: Cyber-physical system designs revisit semiconductor technology. 1-4 - Ka-Meng Lei
A μNMR CMOS transceiver using a butterfly-coil input for integration with a digital microfluidic device inside a portable magnet. 1-4 - Yoshisato Yokoyama, Yuichiro Ishii, Toshihiro Inada, Koji Tanaka, Miki Tanaka, Yoshiki Tsujihashi, Koji Nii:
A cost effective test screening method on 40-nm 4-Mb embedded SRAM for low-power MCU. 1-4 - Jie Zhang, Hong Zhang, Ruizhi Zhang, Jiangtao Xu, Yang Zhao, Mudan Zhang, Jia Li:
A mixed-signal ASIC for triple-chamber cardiac pacemakers with heart resistance measurement. 1-4 - Woo-Rham Bae
A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS. 1-4 - Chia-Liang Tai, Alan Roth, Eric G. Soenen:
A digital low drop-out regulator with wide operating range in a 16nm FinFET CMOS process. 1-4 - Zule Xu, Masaya Miyahara, Akira Matsuzawa:
A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise. 1-4 - Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa:
A fully-integrated, high-conversion-ratio and dual-output voltage boost converter with MPPT for low-voltage energy harvesting. 1-4 - Li-Cheng Chu, Te-Fu Yang, Ru-Yu Huang, Yi-Ping Su, Chiun-He Lin, Chin-Long Wey, Ke-Horng Chen
200nA low quiescent current deep-standby mode in 28nm DC-DC buck converter for active implantable medical devices. 1-4 - Saurabh Agarwal, Mark Ingels, Michal Rakowski, Marianna Pantouvaki, Michiel Steyaert
Wavelength locking of a Si ring modulator using an integrated drop-port OMA monitoring circuit. 1-4 - Mahmoud Saadat, Boris Murmann
A 0.6 V-2.4 V input, fully integrated reconfigurable switched-capacitor DC-DC converter for energy harvesting sensor tags. 1-4 - Chan-Hsiang Weng, Wei-Hsiang Huang, Erkan Alpman, Tsung-Hsien Lin
A 13-MHz 68-dB SNDR CTDSM using SAB loop filter and interpolating flash quantizer with random-skip IDWA function in 90-nm CMOS. 1-4
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