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Sidharta Andalam
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2020 – today
- 2021
- [i7]HeeJong Park, Arvind Easwaran, Sidharta Andalam:
Challenges in Digital Twin Development for Cyber-Physical Production Systems. CoRR abs/2102.03341 (2021) - 2020
- [i6]HeeJong Park, Arvind Easwaran, Sidharta Andalam:
TiLA: Twin-in-the-Loop Architecture for Cyber-Physical Production Systems. CoRR abs/2003.09370 (2020) - [i5]Sidharta Andalam, Daniel Jun Xian Ng, Arvind Easwaran, Karthik Thangamariappan:
Contract-based Methodology for Developing Resilient Cyber-Infrastructure in the Industry 4.0 Era. CoRR abs/2004.04442 (2020) - [i4]Sidharta Andalam, Daniel Jun Xian Ng, Arvind Easwaran, Karthik Thangamariappan:
CLAIR: A Contract-based Framework for Developing Resilient CPS Architectures. CoRR abs/2004.04444 (2020) - [i3]Daniel Jun Xian Ng, Arvind Easwaran, Sidharta Andalam:
Demo Abstract: Contract-based Hierarchical Resilience Framework for Cyber-Physical Systems. CoRR abs/2004.04477 (2020)
2010 – 2019
- 2019
- [j8]Sidharta Andalam
, Daniel Jun Xian Ng, Arvind Easwaran
Contract-Based Methodology for Developing Resilient Cyber-Infrastructure in the Industry 4.0 Era. IEEE Embed. Syst. Lett. 11(1): 5-8 (2019) - [c20]HeeJong Park, Arvind Easwaran
TiLA: Twin-in-the-Loop Architecture for Cyber-Physical Production Systems. ICCD 2019: 82-90 - [c19]Daniel Jun Xian Ng, Arvind Easwaran
Contract-based hierarchical resilience framework for cyber-physical systems: demo abstract. ICCPS 2019: 324-325 - 2018
- [j7]Weiwei Ai
A Parametric Computational Model of the Action Potential of Pacemaker Cells. IEEE Trans. Biomed. Eng. 65(1): 123-130 (2018) - [j6]Eugene Yip
Towards the Emulation of the Cardiac Conduction System for Pacemaker Validation. ACM Trans. Cyber Phys. Syst. 2(4): 32:1-32:26 (2018) - [c18]HeeJong Park
Challenges in Digital Twin Development for Cyber-Physical Production Systems. CyPhy/WESE 2018: 28-48 - [c17]Sidharta Andalam, Daniel Jun Xian Ng, Arvind Easwaran
CLAIR: A Contract-Based Framework for Developing Resilient CPS Architectures. ISORC 2018: 33-41 - [c16]Sidharta Andalam, Partha S. Roop, Avinash Malik, Mark Trew:
Rethinking the Validation Process for Medical Devices: A Cardiac Pacemaker Case Study. ISORC 2018: 134-137 - 2017
- [j5]Wanli Chang
Memory-Aware Embedded Control Systems Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(4): 586-599 (2017) - [j4]Avinash Malik
Modular Compilation of Hybrid Systems for Emulation and Large Scale Simulation. ACM Trans. Embed. Comput. Syst. 16(5s): 118:1-118:21 (2017) - [j3]Sidharta Andalam, Nathan Allen
A Novel Emulation Model of the Cardiac Conduction System. ACM Trans. Embed. Comput. Syst. 16(5s): 157:1-157:20 (2017) - 2016
- [c15]Sidharta Andalam, Avinash Malik, Partha S. Roop, Mark L. Trew:
Hybrid Automata Model of the Heart for Formal Verification of Pacemakers. ARCH@CPSWeek 2016: 9-17 - [c14]Nathan Allen, Sidharta Andalam, Partha S. Roop, Avinash Malik, Mark Trew, Nitish D. Patel:
Modular code generation for emulating the electrical conduction system of the human heart. DATE 2016: 648-653 - [c13]Matthew M. Y. Kuo, Sidharta Andalam, Partha S. Roop:
Precision timed industrial automation systems. DATE 2016: 1024-1025 - [c12]Sidharta Andalam, Harshavardhan Ramanna, Avinash Malik, Partha S. Roop, Nitish D. Patel, Mark L. Trew:
Hybrid automata models of cardiac ventricular electrophysiology for real-time computational applications. EMBC 2016: 5595-5598 - [i2]Eugene Yip, Sidharta Andalam, Partha S. Roop, Avinash Malik, Mark Trew, Weiwei Ai, Nitish D. Patel:
Towards the Emulation of the Cardiac Conduction System for Pacemaker Testing. CoRR abs/1603.05315 (2016) - 2015
- [i1]Avinash Malik, Partha S. Roop, Sidharta Andalam, Eugene Yip, Mark Trew:
A synchronous rendering of hybrid systems for designing Plant-on-a-Chip (PoC). CoRR abs/1510.04336 (2015) - 2014
- [j2]Sidharta Andalam, Partha S. Roop, Alain Girault, Claus Traulsen:
A Predictable Framework for Safety-Critical Embedded Systems. IEEE Trans. Computers 63(7): 1600-1612 (2014) - [c11]Florian Sagstetter, Sidharta Andalam, Peter Waszecki, Martin Lukasiewycz, Hauke Stähle, Samarjit Chakraborty, Alois C. Knoll
Schedule Integration Framework for Time-Triggered Automotive Architectures. DAC 2014: 20:1-20:6 - 2013
- [c10]Matthew M. Y. Kuo, Partha S. Roop, Sidharta Andalam, Nitish D. Patel:
Precision Timed Embedded Systems Using TickPAD Memory. ACSD 2013: 206-215 - [c9]Jia Jie Wang, Partha S. Roop, Sidharta Andalam:
ILPc: A novel approach for scalable timing analysis of synchronous programs. CASES 2013: 20:1-20:10 - [c8]Martin Lukasiewycz, Sebastian Steinhorst
System architecture and software design for electric vehicles. DAC 2013: 95:1-95:6 - [c7]Sidharta Andalam, Alain Girault, Roopak Sinha
Precise timing analysis for direct-mapped caches. DAC 2013: 148:1-148:10 - 2011
- [c6]Sidharta Andalam, Partha S. Roop, Alain Girault:
Pruning infeasible paths for tight WCRT analysis of synchronous programs. DATE 2011: 204-209 - [c5]Sidharta Andalam, Roopak Sinha
Environment Modelling for Tighter Timing Analysis of Synchronous Programs. DELTA 2011: 150-155 - 2010
- [c4]Sidharta Andalam, Partha S. Roop, Alain Girault:
Deterministic, predictable and light-weight multithreading using PRET-C. DATE 2010: 1653-1656 - [c3]Sidharta Andalam, Partha S. Roop, Alain Girault:
Predictable multithreading of embedded applications using PRET-C. MEMOCODE 2010: 159-168
2000 – 2009
- 2009
- [j1]Simon Yuan, Li Hsien Yoong, Sidharta Andalam, Partha S. Roop, Zoran Salcic
A New Multithreaded Architecture Supporting Direct Execution of Esterel. EURASIP J. Embed. Syst. 2009 (2009) - [c2]Partha S. Roop, Sidharta Andalam, Reinhard von Hanxleden, Simon Yuan, Claus Traulsen:
Tight WCRT analysis of synchronous C programs. CASES 2009: 205-214 - 2008
- [c1]Simon Yuan, Sidharta Andalam, Li Hsien Yoong, Partha S. Roop, Zoran A. Salcic
STARPro - A new multithreaded direct execution platform for Esterel. SLAP@ETAPS 2008: 37-55
Coauthor Index
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