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CASES 2013: Montreal, QC, Canada
- International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2013, Montreal, QC, Canada, September 29 - October 4, 2013. IEEE 2013, ISBN 978-1-4799-1400-5
- Anup Das
, Akash Kumar
Aging-aware hardware-software task partitioning for reliable reconfigurable multiprocessor systems. 1:1-1:10 - Gabriel L. Nazar, Leonardo P. Santos
Scrubbing unit repositioning for fast error repair in FPGAs. 2:1-2:10 - Robert J. Halstead, Walid A. Najjar
Compiled multithreaded data paths on FPGAs for dynamic workloads. 3:1-3:10 - Daniel Cordes, Michael Engel, Olaf Neugebauer, Peter Marwedel:
Automatic Extraction of pipeline parallelism for embedded heterogeneous multi-core platforms. 4:1-4:10 - Lars Schor, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele:
Expandable process networks to efficiently specify and explore task, data, and pipeline parallelism. 5:1-5:10 - Thierry Lepley, Pierre G. Paulin, Eric Flamand:
A novel compilation approach for image processing graphs on a many-core platform with explicitly managed memory. 6:1-6:10 - Michael R. Jantz, Prasad A. Kulkarni:
Exploiting phase inter-dependencies for faster iterative compiler optimization phase order searches. 7:1-7:10 - BaekGyu Kim
Platform-dependent code generation for embedded real-time software. 8:1-8:10 - Vasileios Porpodas, Marcelo Cintra:
CAeSaR: Unified cluster-assignment scheduling and communication reuse for clustered VLIW processors. 9:1-9:10 - Lovic Gauthier, Shinya Ueno, Koji Inoue:
Hybrid compile and run-time memory management for a 3D-stacked reconfigurable accelerator. 10:1-10:10 - Fazal Hameed
Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies. 11:1-11:10 - Mengting Yuan, Chun Jason Xue
Minimizing code size via page selection optimization on partitioned memory architectures. 12:1-12:10 - Jason Clemons
EVA: An efficient vision architecture for mobile systems. 13:1-13:10 - Manuel Mohr, Artjom Grudnitsky, Tobias Modschiedler, Lars Bauer, Sebastian Hack, Jörg Henkel:
Hardware acceleration for programs in SSA form. 14:1-14:10 - Mihai Pricopi, Thannirmalai Somu Muthukaruppan, Vanchinathan Venkataramani, Tulika Mitra
Power-performance modeling on asymmetric multi-cores. 15:1-15:10 - Michael Bedford Taylor:
Bitcoin and the age of Bespoke Silicon. 16:1-16:10 - Karthikeyan Sankaralingam:
Dynamic hardware specialization-using moore's bounty without burning the chip down. 17:1 - Andrew Canis, Jongsok Choi, Blair Fort, Ruolong Lian, Qijing Huang
From software to accelerators with LegUp high-level synthesis. 18:1-18:9 - Jiunn-Yeu Chen, Bor-Yeh Shen, Quan-Huei Ou, Wuu Yang, Wei-Chung Hsu
Effective code discovery for ARM/Thumb mixed ISA binaries in a static binary translator. 19:1-19:10 - Jia Jie Wang, Partha S. Roop, Sidharta Andalam:
ILPc: A novel approach for scalable timing analysis of synchronous programs. 20:1-20:10 - Prasenjit Chakraborty, Preeti Ranjan Panda:
SPM-Sieve: A framework for assisting data partitioning in scratch pad memory based systems. 21:1-21:10 - Hao Chen, Chengmo Yang:
Fault detection and recovery efficiency co-optimization through compile-time analysis and runtime adaptation. 22:1-22:10 - Man Wang, Zhiyuan Li:
Global property violation detection and diagnosis for wireless sensor networks. 23:1-23:10 - Xian Zhang, Chao Zhang, Guangyu Sun, Jia Di, Tao Zhang:
An efficient run-time encryption scheme for non-volatile main memory. 24:1-24:10 - Clas A. Jacobson, Richard Schooler, Michel Laurence:
Cyber physical systems: Systems engineering of industrial embedded systems - Barriers, enablers and opportunities. 1-3 - Zeljko Zilic:
Tutorial: Methodologies and tools for embedded multisensory systems based on ARM cortex M processors. 1-8
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