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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 16
Volume 16, Number 1, January 1997
- Rolf Drechsler
, Bernd Becker
Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions. 1-5 - Rohini Gupta, Byron Krauter, Lawrence T. Pileggi:
Transmission line synthesis via constrained multivariable optimization. 6-19 - Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu:
Routing for symmetric FPGAs and FPICs. 20-31 - Shashidhar Thakur, Yao-Wen Chang
Algorithms for an FPGA switch module routing problem with application to global routing. 32-46 - Andrew D. Brown, Keith Richard Baker, Alan Christopher Williams:
On-line testing of statically and dynamically scheduled synthesized systems. 47-57 - Chieh-Yuan Chao, Hung-Jen Lin, L. Miler:
Optimal testing of VLSI analog circuits. 58-77 - Ankan K. Pramanick, Sudhakar M. Reddy:
On the fault coverage of gate delay fault detecting tests. 78-94 - Rohini Gupta, Bogdan Tutuianu, Lawrence T. Pileggi:
The Elmore delay as a bound for RC trees with generalized input signals. 95-104 - Tolga Soyata
Incorporating interconnect, register, and clock distribution delays into the retiming process. 105-120 - José Monteiro
Estimation of average switching activity in combinational logic circuits using symbolic simulation. 121-127
Volume 16, Number 2, February 1997
- Florin Balasa, Francky Catthoor, Hugo De Man:
Practical solutions for counting scalars and dependences in ATOMIUM-a memory management system for multidimensional signal processing. 133-145 - Nelson L. Passos, Edwin Hsing-Mean Sha, Liang-Fang Chao:
Multidimensional interleaving for synchronous circuit design optimization. 146-159 - Kuo-Hua Wang, TingTing Hwang:
Boolean matching for incompletely specified functions. 160-168 - Ali Dasdan, Cevdet Aykanat:
Two novel multiway circuit partitioning algorithms using relaxed locking. 169-178 - Yuh-Sheng Lee, Allen C.-H. Wu:
A performance and routability-driven router for FPGAs considering path delays. 179-185 - Dinesh P. Mehta
Corner stitching for simple rectilinear shapes [VLSI layouts]. 186-198 - Heinz Hoenigschmid, Mitiko Miura-Manausch, Odin Prigge, Alexander Rahm, Dominique Savignac:
Optimization of advanced MOS technologies for narrow distribution of circuit performance. 199-204 - John O'Leary, Geoffrey Brown:
Synchronous emulation of asynchronous circuits. 205-209 - Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi:
Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets. 210-215
Volume 16, Number 3, March 1997
- Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell, John Moondanos:
Automatic verification of implementations of large circuits against HDL specifications. 217-228 - Liang-Fang Chao, Andrea S. LaPaugh, Edwin Hsing-Mean Sha:
Rotation scheduling: a loop pipelining algorithm. 229-239 - Rajesh K. Gupta, Giovanni De Micheli:
Specification and analysis of timing constraints for embedded systems. 240-256 - Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri:
KGPMIN: an efficient multilevel multioutput AND-OR-XOR minimizer. 257-265 - Wolfgang Kunz, Dominik Stoffel, Prem R. Menon:
Logic optimization and equivalence checking by implication analysis. 266-281 - Wai-Kei Mak, Martin D. F. Wong
On optimal board-level routing for FPGA-based logic emulation. 282-289 - Ashok Vittal, Malgorzata Marek-Sadowska:
Crosstalk reduction for VLSI. 290-298 - Shung-Chih Chen, Jer-Min Jou:
Diagnostic fault simulation for synchronous sequential circuits. 299-308 - Dimitrios Kagaris, Spyros Tragoudas, Dimitrios Karayiannis:
Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms. 309-315 - Shiuann-Shiuh Lin, Yuh-Ju Lin, TingTing Hwang:
Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure. 316-320 - Alicja Pierzynska, Slawomir Pilarski:
Pitfalls in delay fault testing. 321-329
Volume 16, Number 4, April 1997
- Gustavo E. Téllez, Majid Sarrafzadeh:
Minimal buffer insertion in clock trees with skew and slew rate constraints. 333-342 - Ming-Jer Chen, Jib-Shin Ho:
A three-parameters-only MOSFET subthreshold current CAD model considering back-gate bias and process variation. 343-352 - Maria Cristina Vecchi, Jan Mohring, Massimo Rudan:
An efficient solution scheme for the spherical-harmonics expansion of the Boltzmann transport equation [MOS transistors]. 353-361 - M. Hira, Dipankar Sarkar:
Verification of Tempura specification of sequential circuits. 362-375 - Kai Zhu, Martin D. F. Wong
Clock skew minimization during FPGA placement. 376-385 - Satoshi Tazawa, Katsuyuki Ochiai, Seitaro Matsuo, Shigeru Nakajima:
A high-speed 2-D topography simulator based on a pixel model. 386-397 - John A. Chandy
An evaluation of parallel simulated annealing strategies with application to standard cell placement. 398-410 - Jason Cong, Patrick H. Madden:
Performance-driven routing with multiple sources. 410-419 - Arlynn W. Smith, Joseph W. Parks Jr., Joe N. Haralson III, Kevin F. Brennan:
A smoothed boundary condition for reducing nonphysical field effects. 420-423
Volume 16, Number 5, May 1997
- Ajoy Opal:
The transition matrix for linear circuits. 427-436 - Eyad Abou-Allam, Tajinder Manku:
A small-signal MOSFET model for radio frequency IC applications. 437-447 - Gianpiero Cabodi, Paolo Camurati:
Symbolic FSM traversals based on the transition relation. 448-457 - Seong Yong Ohm, Fadi J. Kurdahi
A unified lower bound estimation technique for high-level synthesis. 458-472 - Jürgen Teich, Lothar Thiele, Sundararajan Sriram, Michael Martin:
Performance analysis and optimization of mixed asynchronous synchronous systems. 473-484 - Mustafa Celik, Andreas C. Cangellaris:
Simulation of multiconductor transmission lines using Krylov subspace order-reduction techniques. 485-496 - Ajay J. Daga, William P. Birmingham:
Interface finite-state machines: definition, minimization, and decomposition. 497-505 - Yu-Liang Wu, Malgorzata Marek-Sadowska:
Routing for array-type FPGA's. 506-518 - Chih-Chang Lin, Malgorzata Marek-Sadowska:
On designing universal logic blocks and their application to FPGA design. 519-527 - Aiman H. El-Maleh
Behavior and testability preservation under the retiming transformation. 528-543 - Irith Pomeranz, Sudhakar M. Reddy:
LOCSTEP: a logic-simulation-based test generation procedure. 544-554 - Balkrishna Ramkumar, Prithviraj Banerjee:
ProperTEST: a portable parallel test generator for sequential circuits. 555-569
Volume 16, Number 6, June 1997
- Alex Orailoglu:
Microarchitectural synthesis for rapid BIST testing. 573-586 - Shih-Chieh Chang, Kwang-Ting Cheng
Postlayout logic restructuring using alternative wires. 587-596 - Anmol Mathur, C. L. Liu:
Timing-driven placement for regular architectures. 597-608 - Jonathan Babb, Russell Tessier, Matthew Dahl, Silvina Hanono, David M. Hoki, Anant Agarwal:
Logic emulation with virtual wires. 609-626 - Walter Allegretto, Bing Shen, Todd C. Kleckner, Alexander M. Robinson:
Micromachined polysilicon power dissipation: simulation and experiment. 627-637 - Edouard Ngoya, Jean Rousset, Juan J. Obregon:
Newton-Raphson iteration speed-up algorithm for the solution of nonlinear circuit equations in general-purpose CAD programs. 638-644 - T. W. Her, Martin D. F. Wong
Module implementation selection and its application to transistor placement. 645-651 - Andrew Lim
Planar topological routing. 651-656 - Prabir C. Maulik:
Comments on "FPAD: a fuzzy nonlinear programming approach to analog circuit design". 656
Volume 16, Number 7, July 1997
- Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Implicit computation of compatible sets for state minimization of ISFSMs. 657-676 - Tiziano Villa, Timothy Kam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Explicit and implicit algorithms for binate covering problems. 677-691 - Tiziano Villa, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Symbolic two-level minimization. 692-708 - Lars W. Hagen, Andrew B. Kahng:
Combining problem reduction and adaptive multistart: a new technique for superior iterative partitioning. 709-717 - Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
Analytical estimation of signal transition activity from word-level statistics. 718-733 - Kevin J. Kerns, Andrew T. Yang:
Stable and efficient reduction of large, multiport RC networks by pole analysis via congruence transformations. 734-744 - Karim Arabi, Bozena Kaminska:
Testing analog and mixed-signal integrated circuits using oscillation-test method. 745-753 - Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
A fast algorithm for minimizing the Elmore delay to identified critical sinks. 753-759 - Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell, Janak H. Patel:
Improving a nonenumerative method to estimate path delay fault coverage. 759-762 - Peter M. Maurer:
The inversion algorithm for digital simulation. 762-769 - Cecilia Metra, Michele Favalli
On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits. 770-776 - Hsiao-Pin Su, Youn-Long Lin:
A phase assignment method for virtual-wire-based hardware emulation. 776-783 - Nur A. Touba, Edward J. McCluskey:
Logic synthesis of multilevel circuits with concurrent error detection. 783-789
Volume 16, Number 8, August 1997
- Jordi Cortadella
A region-based theory for state assignment in speed-independent circuits. 793-812 - Eric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness:
Logic decomposition during technology mapping. 813-834 - Milton H. Sawasaki, Chantal Ykman-Couvreur, Bill Lin:
Externally hazard-free implementations of asynchronous control circuits. 835-848 - Scott Hauck, Gaetano Borriello:
An evaluation of bipartitioning techniques. 849-866 - Noel Menezes, Ross Baldick, Lawrence T. Pileggi:
A sequential quadratic programming approach to concurrent gate and wire sizing. 867-881 - Chin-Chi Teng, Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang:
iTEM: a temperature-dependent electromigration reliability diagnosis tool. 882-893 - Peter A. Walker, Sumit Ghosh:
On the nature and inadequacies of transport timing delay constructs in VHDL descriptions. 894-915 - Krishnendu Chakrabarty
On the quality of accumulator-based compaction of test responses. 916-922 - Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara:
Compact test sets for high defect coverage. 923-930 - S. Yu, Barrie W. Jervis, Kevin R. Eckersall, Ian M. Bell:
Diagnosis of CMOS op-amps with gate oxide short faults using multilayer perceptrons. 930-935
Volume 16, Number 9, September 1997
- Christoph Wasshuber, Hans Kosina, Siegfried Selberherr
SIMON-A simulator for single-electron tunnel devices and circuits. 937-944 - Douglas M. Blough, Fadi J. Kurdahi
Optimal algorithms for recovery point insertion in recoverable microarchitectures. 945-955 - Scott Hauck, Gaetano Borriello:
Pin assignment for multi-FPGA systems. 956-964 - Ashok Vittal, Malgorzata Marek-Sadowska:
Low-power buffered clock tree design. 965-975 - Hannah Honghua Yang, Martin D. F. Wong
Circuit clustering for delay minimization under area and pin constraints. 976-986 - Alaaeldin A. Amin, Mohamed Y. Osman, Radwan E. Abdel-Aal, Husni Al-Muhtaseb
New fault models and efficient BIST algorithms for dual-port memories. 987-1000 - Indradeep Ghosh
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. 1001-1014 - Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo
Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR. 1015-1024 - Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen:
Identifying invalid states for sequential circuit test generation. 1025-1033 - Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann:
A genetic algorithm framework for test generation. 1034-1044 - Xiaoling Sun, Micaela Serra:
On-line and off-line testing with shared resources: a new BIST approach. 1045-1056
Volume 16, Number 10, October 1997
- Joel R. Phillips, Jacob K. White:
A precorrected-FFT method for electrostatic analysis of complicated 3-D structures. 1059-1072 - Qicheng Yu, Carl Sechen:
Efficient approximation of symbolic network functions using matroid intersection algorithms. 1073-1081 - P. Douglas Yoder, Klaus Gärtner, Ulrich Krumbein, Wolfgang Fichtner:
Optimized terminal current calculation for Monte Carlo device simulation. 1082-1087 - Irith Pomeranz, Sudhakar M. Reddy:
On error correction in macro-based circuits. 1088-1100 - R. Iris Bahar
Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths. 1101-1115 - Nuno C. G. Horta
Algorithm-driven synthesis of data conversion architectures. 1116-1135 - Enrico Macii, Bernard Plessier, Fabio Somenzi:
Formal verification of digital systems by automatic reduction of data paths. 1136-1156 - Srimat T. Chakradhar, Anand Raghunathan
Bottleneck removal algorithm for dynamic compaction in sequential circuits. 1157-1172 - Chen-Yang Pan, Kwang-Ting Cheng
Pseudorandom testing for mixed-signal circuits. 1173-1185 - Marcello Dalpasso
A method for increasing the IDDQ testability. 1186-1188 - Wen-Jong Fang, Allen C.-H. Wu:
A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations. 1188-1195 - Henrik Floberg, Sven Mattisson:
Symbolic analysis of switched-capacitor networks using compacted nodal analysis in the s-domain. 1196-1199 - Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng:
On implementation choices for iterative improvement partitioning algorithms. 1199-1205 - Noriya Kobayashi, Sharad Malik
Delay abstraction in combinational logic circuits. 1205-1212 - Chor Ping Low, Hon Wai Leong:
On the reconfiguration of degradable VLSI/WSI arrays. 1213-1221 - Wai-Kei Mak, Martin D. F. Wong
Minimum replication min-cut partitioning. 1221-1227 - Anand L. Pardhanani, Graham F. Carey:
A mapped Scharfetter-Gummel formulation for the efficient simulation of semiconductor device models. 1227-1233
Volume 16, Number 11, November 1997
- Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell:
On variable clock methods for path delay testing of sequential circuits. 1237-1249 - Ming Qu, M. A. Styblinski:
Parameter extraction for statistical IC modeling based on recursive inverse approximation. 1250-1259 - Anand Raghunathan
SCALP: an iterative-improvement-based low-power data path synthesis system. 1260-1277 - Maurizio Damiani:
The state reduction of nondeterministic finite-state machines. 1278-1291 - Uwe Hübner, Heinrich Theodor Vierhaus, Raul Camposano:
Partitioning and analysis of static digital CMOS circuits. 1292-1310 - Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Theory and algorithms for state minimization of nondeterministic FSMs. 1311-1322 - Xianlong Hong, Tianxiong Xue, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh:
TIGER: an efficient timing-driven global router for gate array and standard cell layout design. 1323-1331 - Majid Sarrafzadeh, David A. Knol, Gustavo E. Téllez:
A delay budgeting algorithm ensuring maximum flexibility in placement. 1332-1341 - Wern-Jieh Sun, Carl Sechen:
A parallel standard cell placement algorithm. 1342-1357 - Katarzyna Radecka, Janusz Rajski, Jerzy Tyszer:
Arithmetic built-in self-test for DSP cores. 1358-1369 - Srimat T. Chakradhar, Steven G. Rothweiler, Vishwani D. Agrawal:
Redundancy removal and test generation for circuits with non-Boolean primitives. 1370-1377 - Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu:
Design of minimum and uniform bipartites for optimum connection blocks of FPGA. 1377-1383 - C. S. Murthy, M. Gall:
Process variation effects on circuit performance: TCAD simulation of 256-Mbit technology [DRAMs]. 1383-1389
Volume 16, Number 12, December 1997
- Kumar N. Lalgudi, Marios C. Papaefthymiou:
Retiming edge-triggered circuits under general delay models. 1393-1408 - Wei Long, Li-heng Lee, Erhard Kohn, Ken K. Chin:
Analytical modeling of dual-gate HFET's. 1409-1417 - Tianxiong Xue, Ernest S. Kuh, Dongsheng Wang:
Post global routing crosstalk synthesis. 1418-1430 - Heinrich Kirchauer, Siegfried Selberherr
Rigorous three-dimensional photoresist exposure and development simulation over nonplanar topography. 1431-1438 - Martin Bächtold, Markus Emmenegger, Jan G. Korvink
An error indicator and automatic adaptive meshing for electrostatic boundary element simulations. 1439-1446 - Wendemagegnehu T. Beyene, José E. Schutt-Ainé:
Transient analysis of diode switching circuits using asymptotic waveform evaluation. 1447-1453 - Mike Chou, Jacob K. White:
Efficient formulation and model-order reduction for the transient simulation of three-dimensional VLSI interconnect. 1454-1476 - Yau-Tsun Steven Li, Sharad Malik
Performance analysis of embedded software using implicit path enumeration. 1477-1487 - Sujit Dey, Miodrag Potkonjak:
Nonscan design-for-testability techniques using RT-level design information. 1488-1506 - Andrew B. Kahng, Sudhakar Muddu:
An analytical delay model for RLC interconnects. 1507-1514 - Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng:
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. 1514-1521
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