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VTS 1996: Princeton, NJ, USA
- 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA. IEEE Computer Society 1996, ISBN 0-8186-7304-4
Design for Testability
- Nur A. Touba, Edward J. McCluskey:
Test point insertion based on path tracing. 2-8 - R. D. (Shawn) Blanton, John P. Hayes:
Design of a fast, easily testable ALU. 9-16 - Fidel Muradali, Janusz Rajski:
A self-driven test structure for pseudorandom testing of non-scan sequential circuits. 17-25 - Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno
, Paolo Prinetto, Matteo Sonza Reorda
Scan insertion criteria for low design impact. 26-31 - Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal:
Segment delay faults: a new fault model. 32-41
Testability of Analog Circuits
- Diego Vázquez, José L. Huertas, Adoración Rueda:
Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design. 42-47 - Eric Felt, Alberto L. Sangiovanni-Vincentelli:
Optimization of analog IC test structures. 48-53 - Michel Renovell, Florence Azaïs, Yves Bertrand:
The multi-configuration: A DFT technique for analog circuits. 54-59 - Mehdi Ehsanian, Bozena Kaminska, Karim Arabi:
A new digital test approach for analog-to-digital converter testing. 60-65 - J. van Spaandonk, Tom A. M. Kevenaar:
Iterative test-point selection for analog circuits. 66-73
Synthesis for Testability
- Subhrajit Bhattacharya, Sujit Dey:
H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads. 74-80 - X. Wendling, Raphaël Rochet, Régis Leveugle:
Standard and ROM-based synthesis of FSMs with control flow checking capabilities. 81-86 - Robert B. Norwood, Edward J. McCluskey:
Synthesis-for-scan and scan chain ordering. 87-92 - Yuan Lu, Irith Pomeranz:
Synchronization of large sequential circuits by partial reset. 93-98 - M. Miegler, Werner Wolz:
Development of test programs in a virtual test environment. 99-105
IDDQ Testing
- Antoni Ferré, Joan Figueras:
On estimating bounds of the quiescent current for IDDQ testin. 106-111 - Anne E. Gattiker, Wojciech Maly:
Current signatures [VLSI circuit testing]. 112-117 - Stephan P. Athan, David L. Landis, Sami A. Al-Arian:
A novel built-in current sensor for IDDQ testing of deep submicron CMOS ICs. 118-123 - Salvador Manich, Michael Nicolaidis, Joan Figueras:
Enhancing realistic fault secureness in parity prediction array arithmetic operators by IDDQ monitoring. 124-129 - Hari Balachandran, D. M. H. Walker:
Improvement of SRAM-based failure analysis using calibrated Iddq testing. 130-137
On-Line Testing
- Egor S. Sogomonyan, Michael Gössel:
Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems. 138-144 - Cecilia Metra, Michele Favalli, Bruno Riccò:
Embedded two-rail checkers with on-line testing ability. 145-150 - Nikolaos Gaitanis, Dimitris Gizopoulos, Antonis M. Paschalis, Panagiotis Kostarakis:
An asynchronous totally self-checking two-rail code error indicator. 151-156 - Steven S. Gorshe, Bella Bose:
A self-checking ALU design with efficient codes. 157-161 - Vladimir V. Saposhnikov, Alexej Dmitriev, Michael Gössel, Valerij V. Saposhnikov:
Self-dual parity checking-A new method for on-line testing. 162-168 - Jean-Luis Dufour:
Safety computations in integrated circuits. 169-173
Fault Diagnosis and Dictionaries
- Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs:
Full fault dictionary storage based on labeled tree encoding. 174-179 - John W. Sheppard, William R. Simpson:
Improving the accuracy of diagnostics provided by fault dictionaries. 180-185 - Masaru Sanada:
A CAD-based approach to failure diagnosis of CMOS LSI's using abnormal Iddq. 186-191 - Sreejit Chakravarty:
A sampling technique for diagnostic fault simulation. 192-197 - Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs:
Dynamic diagnosis of sequential circuits based on stuck-at faults. 198-203 - Wei-Kang Huang, Xiao-Tao Chen, Fabrizio Lombardi:
On the diagnosis of programmable interconnect systems: Theory and application. 204-211
Panel Session
- Robert C. Aitken, J. Hutcheson, N. Murthy, Phil Nigh, Nicholas Sporck:
Volume Manufacturing - ICs and Boards: DFT to the Rescue? 212-213 - Bozena Kaminska, Tad A. Kwasniewski, Linda S. Milor, G. Roberts, P. Flahive, Jérôme Wojcik:
Is High Frequency Analog DFT Possible? 214-215
Sequential Circuit Testing
- Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Automatic test generation using genetically-engineered distinguishing sequences. 216-223 - Krishna B. Rajan, David E. Long, Miron Abramovici:
Increasing testability by clock transformation (getting rid of those darn states). 224-230 - Robert H. Klenke, James H. Aylor, Joseph M. Wolf:
An analysis of fault partitioning algorithms for fault partitioned ATPG. 231-239 - Martin Keim, Bernd Becker, Birgitta Stenner:
On the (non-)resetability of synchronous sequential circuits. 240-245 - Jalal A. Wehbeh, Daniel G. Saab:
Initialization of sequential circuits and its application to ATPG. 246-253
Multi-Chip Modules and Memory Testing
- T. Raju Damarla, Moon J. Chung, Wei Su, Gerald T. Michael:
Faulty chip identification in a multi chip module system. 254-259 - Bruce C. Kim, Abhijit Chatterjee, Madhavan Swaminathan:
Low-cost diagnosis of defects in MCM substrate interconnections. 260-265 - Vladimir A. Koval, Dmytro V. Fedasyuk:
The MCM's thermal testing. 266-271 - Ad J. van de Goor, Georgi Gaydadjiev
March LR: a test for realistic linked faults. 272-280 - M. P. Kluth, François Simon, Jean-Yves Le Gall, E. Müller:
Design of a fault tolerant 100 Gbits solid-state mass memory for satellite. 281-287
Delay Fault Testing
- Prasanti Uppaluri, Uwe Sparmann, Irith Pomeranz:
On minimizing the number of test points needed to achieve complete robust path delay fault testability. 288-295 - S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
A new test pattern generation method for delay fault testing. 296-301 - Valery A. Vardanian:
On completely robust path delay fault testable realization of logic functions. 302-307 - Sophie Crépaux-Motte, Mireille Jacomino, René David:
An algebraic method for delay fault testing. 308-315 - Mukund Sivaraman, Andrzej J. Strojwas:
A diagnosability metric for parametric path delay faults. 316-323
Non-Traditional Testing
- Peter Wohl, John A. Waicukauski, Matthew Graf:
Testing "untestable" faults in three-state circuits. 324-331 - Jonathan T.-Y. Chang, Edward J. McCluskey:
Quantitative analysis of very-low-voltage testing. 332-337 - Michel Renovell, P. Huc, Yves Bertrand:
Bridging fault coverage improvement by power supply control. 338-343 - Yuyun Liao, D. M. H. Walker:
Optimal voltage testing for physically-based faults. 344-353 - Abhijit Chatterjee, Rathish Jayabharathi, Pankaj Pant, Jacob A. Abraham:
Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages. 354-361
Panel Session
- R. L. Campbell, P. Kuekes, David Y. Lepejian, Wojciech P. Maly, Michael Nicolaidis, Alex Orailoglu:
Can Defect-Tolerant Chips Better Meet the Quality Challenge? 362-363 - Bernd Koenemann, J. Monzel, T. Powell, N. Saxena, K. Wagner:
Design Validation: Formal Verification vs. Simulation vs. Functional Testing. 364-365 - Bernd Koenemann, J. Monzel, T. Powell, N. Saxena, K. Wagner:
BIST: Advantages or Limitations? 366-367
Advances in Built-In Self-Test
- Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska:
Design and performance of CMOS TSPC cells for high speed pseudo random testing. 368-373 - Dimitrios Kagaris, Spyros Tragoudas:
Generating deterministic unordered test patterns with counters. 374-379 - Albrecht P. Stroele:
Test response compaction using arithmetic functions. 380-386 - Charles E. Stroud, Srinivasa Konala, Ping Chen, Miron Abramovici:
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!). 387-392 - Nur A. Touba, Edward J. McCluskey:
Applying two-pattern tests using scan-mapping. 393-399
Fault Modeling and Defect Coverage
- Theo J. Powell:
Consistently dominant fault model for tristate buffer nets. 400-404 - Jitendra Khare, Wojciech Maly, Nathan Tiday:
Fault characterization of standard cell libraries using inductive contamination. 405-413 - Peter Dahlgren, Peter Lidén:
A fault model for switch-level simulation of gate-to-drain shorts. 414-421 - Haluk Konuk, F. Joel Ferguson:
An unexpected factor in testing for CMOS opens: the die surface. 422-429 - Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara:
On the effects of test compaction on defect coverage. 430-437
Fault Simulation and Test Generation
- Minesh B. Amin, Bapiraju Vinnakota:
ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator. 438-443 - Anastasios Vergis, Carlos Tobon:
Testing trees for multiple faults. 444-449 - Wei-Kang Huang, Fabrizio Lombardi:
An approach for testing programmable/configurable field programmable gate arrays. 450-455 - Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel:
Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits. 456-462 - Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya:
Isomorph-redundancy in sequential circuits. 463-469
Mixed-Signal Test Techniques
- Hong Helena Zheng, Ashok Balivada, Jacob A. Abraham:
A novel test generation approach for parametric faults in linear analog circuits . 470-475 - Karim Arabi, Bozena Kaminska:
Oscillation-test strategy for analog and mixed-signal integrated circuits. 476-482 - Bapiraju Vinnakota:
Monitoring power dissipation for fault detection. 483-488 - Chen-Yang Pan, Kwang-Ting Cheng:
Implicit functional testing for analog circuits. 489-494 - F. Mohamed, M. Manzouki, Anton Biasizzo, Franc Novak:
Analog circuit simulation and troubleshooting with FLAMES. 495-501
Panel Session
- Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma:
Delay Fault Testing: How Robust are Our Models? 502-503 - J. Braden, K. Brough, J. Evans, Martin P. McHugh, G. Young:
Board-Level BIST. 504-505 - J. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard:
Hardware-Software Co-Design for Test: It's the Last Straw! 506-507
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