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8th FPL 1998: Tallinn, Estonia
- Reiner W. Hartenstein, Andres Keevallik:
Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL'98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings. Lecture Notes in Computer Science 1482, Springer 1998, ISBN 3-540-64948-4
Design Methods
- David Robinson, Gordon Charles McGregor, Patrick Lysaght:
New CAD Framework Extends Simulation of Dynamically Reconfigurable Logic. 1-8 - Wayne Luk, Steve McKeever:
Pebble: A Language for Parametrised and Reconfigurable Hardware Design. 9-18 - Valery Sklyarov, Ricardo Sal Monteiro, Nuno Lau, Andreia Melo, Arnaldo S. R. Oliveira, Konstantin Kondratjuk:
Integrated Development Environment for Logic Synthesis Based on Dynamically Reconfigurable FPGAs. 19-28 - Reiner W. Hartenstein, Michael Herz, Frank Gilbert:
Designing for Xilinx XC6200 FPGAs. 29-38
General Aspects
- Jürgen Becker, Andreas Kirschbaum, Frank-Michael Renner, Manfred Glesner:
Perspectives of Reconfigurable Computing in Research, Industry and Education. 39-48 - Gordon J. Brebner
:
Field-Programmable Logic: Catalyst for New Computing Paradigms. 49-58 - Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung:
Run-Time Management of Dynamically Recongigurable Designs. 59-68 - Marco Platzner, Giovanni De Micheli:
Acceleration of Satisfiability Algorithms by Reconfigurable Hardware. 69-78
Prototyping/Simulation
- Jörn Stohmann, Klaus Harbich, Markus Olbrich, Erich Barke:
An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping. 79-88 - Helena Krupnova, Vu DucAnh Dinh, Gabriele Saucier:
A Knowledge-Based System for Prototyping on FPFAs. 89-98 - Robert Macketanz, Wolfgang Karl:
JVX - A Rapid Prototyping System Based on Java and FPGAs. 99-108 - Joy Shetler, Brian Hemme, Chia Yang, Christopher Hinsz:
Prototyping New ILP Architectures Using FPGAs. 109-118
Development Methods
- Samary Baranov:
CAD System for ASM and FSM Synthesis. 119-128 - John Marty Emmert, Akash Randhar, Dinesh Bhatia
Fast Floorplanning for FPGAs. 129-138 - Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. 139-148 - Gunter Haug, Wolfgang Rosenstiel:
Reconfigurable Hardware as Shared Resource in Multipurpose Computers. 149-158
Accelerators
- Scott H. Robinson, Michael P. Caffrey, Mark E. Dunham:
Reconfigurable Computer Array: The Bridge between High Speed Sensors and Low Speed Computing. 159-168 - Wayne Luk, P. Andreou, Arran Derbyshire, Florent Dupont de Dinechin, J. Rice, Nabeel Shirazi, D. Siganos:
A Reconfigurable Engine for Real-Time Video Processing. 169-178 - Frank-Michael Renner, Jürgen Becker, Manfred Glesner:
An FPFA Implementation of a Magnetic Bearing Controller for Mechatronic Applications. 179-188
System Architectures
- Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger:
Exploiting Contemporary Memory Techniques in Reconfigurable Accelerators. 189-198 - Adam Donlin:
Self Modifying Circuitry - A Platform for Tractable Virtual Circuitry. 199-208 - Dinesh Bhatia
REACT: Reactive Environment for Runtime Reconfiguration. 209-217
Applications (1)
- Stephen Charlwood, Philip James-Roxby:
Evaluation of the XC6200-series Architecture for Cryptographic Applications. 218-227 - Ali Zakerolhosseini, Peter Lee, Ed Horne:
An FPFA Based Object Recognition Machine. 228-237 - Georg Acher, Wolfgang Karl, Markus Leberecht:
PCI-SCI Protocol Translations: Applying Microprogramming Concepts to FPGAs. 238-247 - Timothy J. Callahan, John Wawrzynek:
Instruction-Level Parallelism for Reconfigurable Computing. 248-257
Hardware/Software Codesign
- Gordon Charles McGregor, David Robinson, Patrick Lysaght:
A Hardwar/Software Co-design Environment for Reconfigurable Logic Systems. 258-267 - Kiran Bondalapati, Viktor K. Prasanna:
Mapping Loops onto Reconfigurable Architectures. 268-277 - Sameh W. Asaad, Kevin W. Warren:
Speed Optimization of the ALR Circuit Using an FPGA with Embedded RAM: A Design Experience. 278-287
System Development
- Rainer Kress, Andreas Pyttel:
High-Level Synthesis for Dynamically Reconfigurable Hardware/Software Systems. 288-297 - Nicholas McKay, Satnam Singh:
Dynamic Specialisation of XC6200 FPGAs by Parial Evaluation. 298-307 - Steve Guccione:
WebScope: A Circuit Debug Tool. 308-315
Algorithms on FPGAs
- Dominique Lavenier, Yannick Saouter
Computing Goldbach Partitions Using Pseudo-random Bit Generator Operators on a FPFA Systolic Array. 316-325 - Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik
Solving Boolean Satisfiability with Dynamic Hardware Configurations. 326-335 - Juri Põldre, Kalle Tammemäe, Marek Mandre:
Modular Exponent Realization on FPGAs. 336-347 - Béla Fehér, Gábor Szedö:
Cost Effective 2×2 Inner Product Processors. 348-355
Applications (2)
- Tsutomu Maruyama, Terunobu Funatsu, Tsutomu Hoshino:
A Field-Programmable Gate-Array System for Evolutionary Computation. 356-365 - Toshiaki Miyazaki, Kazuhiro Shirakawa, Masaru Katayama, Takahiro Murooka, Atsushi Takahara:
A Transmutable Telecom System. 366-375
Tutorial
- Bozidar Radunovic, Veljko M. Milutinovic:
A Survey of Reconfigurable Computing Architectures. 376-385
Miscellaneous
- N. L. Miller, Steven F. Quigley:
A Novel Field Programmable Gat Array Architecture for High Speed Arithmetic Processing. 386-390 - Donald MacVicar, Satnam Singh:
Accelerating DTP with Reconfigurable Computing Engines. 391-395 - Carmen N. Ojeda-Guerra, Roberto Esper-Chaín, M. Estupiñán, Elsa M. Macías
Hardware Mapping of a Parallel Algorithm for Matrix-Vector Multiplication Overlapping Communications and Computations. 396-400 - Gordon J. Brebner
An Interactive Datasheet for the Xilinx XC6200. 401-405 - Neil Woolfries, Patrick Lysaght, Stephen Marshall, Gordon Charles McGregor, David Robinson:
Fast Adaptive Image Processing in FPGAs Using Stack Filters. 406-410 - Sergej Sawitzki, Achim Gratz, Rainer G. Spallek:
Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays. 411-415 - Neil W. Bergmann, Peter R. Sutton:
A High-Performance Computing Module for a Low Earth Orbit Satellite Using Reconfigurable Logic. 416-420 - Shinichi Yamagiwa, Masaaki Ono, Takeshi Yamazaki, Pusit Kulkasem, Masayuki Hirota, Koichi Wada:
Maestro-Link: A High Performance Interconnect for PC Cluster. 421-425 - Tsunemichi Shiozawa, Kiyoshi Oguri, Kouichi Nagami, Hideyuki Ito, Ryusuke Konishi, Norbert Imlig:
A Hardware Implementation of Constraint Satisfaction Problem Based on New Reconfigurable LSI Architecture. 426-430 - Pedro Merino, Juan Carlos López, Margarida F. Jacome:
A Hardwar Operating System for Dynamic Reconfiguration of FPGAs. 431-435 - Elena Cerro-Prada
High Speed Low Level Image Processing on FPGAs Using Distributed Arithmetic. 436-440 - Tien-Toan Do, Holger Kropp, Carsten Reuter, Peter Pirsch:
A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAs. 441-445 - István Vassányi:
Implementing Processor Arrays on FPGAs. 446-450 - Samuel Holmström, Kaisa Sere:
Reconfigurable Hardware - A Study in Codesign. 451-455 - Claude Ackad:
Statechart-Based HW/SW-Codesign of a Multi-FPGA-Board and a Microprocessor. 456-460 - Abdellah Touhafi, Wouter Brissinck, Erik F. Dirkx:
Simulation of ATM Switches Using Dynamically Reconfigurable FPGAs. 461-465 - Tero Rissa, Tommi Mäkeläinen, Jarkko Niittylahti, Jouni Siirtola:
Fast Prototyping Using System Emulators. 466-470 - Andreas Dandalis, Viktor K. Prasanna:
Space-efficient Mapping of 2D-DCT onto Dynamically Configurable Coarse-Grained Architectures. 471-475 - Igor Lemberski, M. Ratniece:
XILINX4000 Architecture-Driven Synthesis for Speed. 476-480 - Valeri Tomachev:
The PLD-Implementation of Boolean Function Characterized by Minimum Delay. 481-484 - A. Abo Shosha, P. Reinhart, F. Rongen:
Reconfigurable PCI-Bus Interface (RPCI). 485-489 - Andrej Trost, Andrej Zemva, Baldomir Zajc:
Programmabel Prototyping System for Image Processing. 490-494 - J. Fischer, C. Müller, H. Kurz:
A Co-simulation Concept for an Efficient Analysis of Complex Logic Designs. 495-499 - Andreas C. Döring, Wolfgang Obelöer, Gunther Lustig:
Programming and Implementation of Reconfigurable Routers. 500-504 - María José Moure
Virtual Instruments Based on Reconfigurable Logic. 505-509 - Christian Siemers, Dietmar P. F. Möller:
The >S<puter: Introducing a Novel Concept for Dispatching Instructions Using Reconfigurable Hardware. 510-514 - Loïc Lagadec, Bernard Pottier:
A 6200 Model and Editor Based on Object Technology. 515-519 - Michael Eisenring, Jürgen Teich:
Interfacing Hardware and Software. 520-524 - James Hwang, Cameron Patterson, S. Mohan, Eric Dellinger, Sujoy Mitra, Ralph Wittig:
Generating Layouts for Self-implementing Modules. 525-529
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