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Gordon J. Brebner
Person information
- affiliation: AMD, San Jose, CA
- affiliation (former): University of Edinburgh, UK
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2020 – today
- 2022
- [c48]Haris Javaid, Ji Yang, Nathania Santoso, Mohit Upadhyay, Sundararajarao Mohan
, Chengchen Hu, Gordon J. Brebner:
Blockchain Machine: A Network-Attached Hardware Accelerator for Hyperledger Fabric. ICDCS 2022: 258-268 - 2021
- [i4]Haris Javaid, Ji Yang, Nathania Santoso, Mohit Upadhyay, Sundararajarao Mohan, Chengchen Hu, Gordon J. Brebner:
Blockchain Machine: A Network-Attached Hardware Accelerator for Hyperledger Fabric. CoRR abs/2104.06968 (2021) - 2020
- [j7]Siyi Qiao, Chengchen Hu, Gordon J. Brebner, Jianhua Zou, Xiaohong Guan:
Adaptable Switch: A Heterogeneous Switch Architecture for Network-Centric Computing. IEEE Commun. Mag. 58(12): 64-69 (2020)
2010 – 2019
- 2019
- [c47]Guanwen Zhong, Haris Javaid, Hassaan Saadat, Lingchao Xu, Chengchen Hu, Gordon J. Brebner:
FastProxy: Hardware and Software Acceleration of Stratum Mining Proxy. CVCBT 2019: 73-76 - [c46]Stephen Ibanez, Gordon J. Brebner
The P4->NetFPGA Workflow for Line-Rate Packet Processing. FPGA 2019: 1-9 - [c45]Stephen Ibanez, Gianni Antichi
Event-Driven Packet Processing. HotNets 2019: 133-140 - [c44]Haris Javaid, Chengchen Hu, Gordon J. Brebner:
Optimizing Validation Phase of Hyperledger Fabric. MASCOTS 2019: 269-275 - [i3]Haris Javaid, Chengchen Hu, Gordon J. Brebner:
Optimizing Validation Phase of Hyperledger Fabric. CoRR abs/1907.08367 (2019) - 2017
- [c43]Huynh Tu Dang, Han Wang, Theo Jepsen, Gordon J. Brebner
Whippersnapper: A P4 Language Benchmark Suite. SOSR 2017: 95-101 - 2015
- [c42]Gordon J. Brebner:
Programmable hardware for software defined networks. ECOC 2015: 1-3 - [c41]Gordon J. Brebner:
Programmable hardware in software defined networking. OFC 2015: 1 - [c40]Gordon J. Brebner:
Programmable hardware for high performance SDN. OFC 2015: 1-3 - [e5]Gordon J. Brebner, Alex Bachmutsky, Chita R. Das:
Proceedings of the Eleventh ACM/IEEE Symposium on Architectures for networking and communications systems, ANCS 2015, Oakland, CA, USA, May 7-8, 2015. IEEE Computer Society 2015, ISBN 978-1-4673-6632-8 [contents] - 2014
- [j6]Gordon J. Brebner
High-Speed Packet Processing using Reconfigurable Computing. IEEE Micro 34(1): 8-18 (2014) - [e4]Viktor K. Prasanna, Gordon J. Brebner, Isaac Keslassy:
Proceedings of the tenth ACM/IEEE symposium on Architectures for networking and communications systems, ANCS 2014, Los Angeles, CA, USA, October 20-21, 2014. ACM 2014, ISBN 978-1-4503-2839-5 [contents] - 2013
- [j5]Christopher E. Neely, Gordon J. Brebner
ReShape: Towards a High-Level Approach to Design and Operation of Modular Reconfigurable Systems. ACM Trans. Reconfigurable Technol. Syst. 6(1): 5:1-5:23 (2013) - 2012
- [c39]Gordon J. Brebner
Softly defined networking. ANCS 2012: 1-2 - [c38]Thilan Ganegedara, Viktor K. Prasanna, Gordon J. Brebner
Optimizing packet lookup in time and space on FPGA. FPL 2012: 270-276 - 2011
- [c37]Michael Attig, Gordon J. Brebner
400 Gb/s Programmable Packet Parsing on a Single FPGA. ANCS 2011: 12-23 - [c36]Gordon J. Brebner:
Reconfigurable Computing for High Performance Networking Applications. ARC 2011: 1 - 2010
- [c35]Christopher E. Neely, Gordon J. Brebner
ShapeUp: A High-Level Design Approach to Simplify Module Interconnection on FPGAs. FCCM 2010: 141-148 - [c34]Christopher E. Neely, Gordon J. Brebner
Flexible and Modular Support for Timing Functions in High Performance Networking Acceleration. FPL 2010: 513-518
2000 – 2009
- 2009
- [c33]Gordon J. Brebner
Packets everywhere: The great opportunity for field programmable technology. FPT 2009: 1-10 - 2008
- [j4]Shuvra S. Bhattacharyya, Gordon J. Brebner
OpenDF: a dataflow toolset for reconfigurable hardware and multicore systems. SIGARCH Comput. Archit. News 36(5): 29-35 (2008) - 2007
- [j3]Gordon J. Brebner
Editorial for the Special Issue on Field Programmable Technology. J. VLSI Signal Process. 47(1): 1-2 (2007) - 2006
- [c32]Chidamber Kulkarni, Gordon J. Brebner
Memory centric thread synchronization on platform FPGAs. DATE 2006: 959-964 - [c31]Michael Attig, Gordon J. Brebner
Systematic Characterization of Programmable Packet Processing Pipelines. FCCM 2006: 195-204 - [c30]Jike Chong, Chidamber Kulkarni, Gordon J. Brebner
Building a flexible and scalable DRAM interface for networking applications on FPGAs. FPGA 2006: 233 - [c29]Chidamber Kulkarni, Gordon J. Brebner
Micro-Coded Datapaths: Populating the Space Between Finite State Machine and Processor. FPL 2006: 1-6 - [e3]Peter M. Athanas, Jürgen Becker, Gordon J. Brebner, Jürgen Teich:
Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006. Dagstuhl Seminar Proceedings 06141, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany 2006 [contents] - [i2]Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas:
06141 Executive Summary -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures 2006 - [i1]Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas:
06141 Abstracts Collection -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures 2006 - 2005
- [c28]Todd S. Sproull, Gordon J. Brebner
Mutable Codesign for Embedded Protocol Processing. FCCM 2005: 299-300 - [c27]Todd S. Sproull, Gordon J. Brebner
Mutable Codesign for Embedded Protocol Processing. FPL 2005: 51-56 - [e2]Gordon J. Brebner, Samarjit Chakraborty, Weng-Fai Wong:
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, FPT 2005, 11-14 December 2005, Singapore. IEEE 2005, ISBN 0-7803-9407-0 [contents] - 2004
- [c26]Gordon J. Brebner
Hyper-Programmable Architectures for Adaptable Networked Systems. ASAP 2004: 328-338 - [c25]Chidamber Kulkarni, Gordon J. Brebner
Mapping a domain specific language to a platform FPGA. DAC 2004: 924-927 - [c24]Philip James-Roxby, Gordon J. Brebner
Time-Critical Software Deceleration in an FCCM. FCCM 2004: 3-12 - [c23]Gordon J. Brebner:
Programmable Logic Has More Computational Power than Fixed Logic. FPL 2004: 404-413 - [c22]Philip James-Roxby, Gordon J. Brebner:
Multithreading in a Hyper-programmable Platform for Networked Systems. FPL 2004: 1017-1021 - [c21]Eric Keller, Gordon J. Brebner
Programming a hyper-programmable architecture for networked systems. FPT 2004: 1-8 - 2003
- [c20]Gordon J. Brebner
Eccentric SoC Architectures as the Future Norm. DSD 2003: 2-9 - [c19]Eric Keller, Gordon J. Brebner, Philip James-Roxby:
Software Decelerators. FPL 2003: 385-395 - [c18]Gordon J. Brebner
Networking on chip with platform FPGAs. FPT 2003: 13-20 - 2002
- [c17]Gordon J. Brebner
Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro. FCCM 2002: 35-44 - [c16]Gordon J. Brebner:
Multithreading for Logic-Centric Systems. FPL 2002: 5-14 - [c15]Gordon J. Brebner
Workshop Introduction. IPDPS 2002 - 2001
- [c14]Gordon J. Brebner
Circlets: Circuitry over the Internet. FCCM 2001: 261-262 - [c13]Gordon J. Brebner, Oliver Diessel:
Chip-Based Reconfigurable Task Management. FPL 2001: 182-191 - [e1]Gordon J. Brebner
Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings. Lecture Notes in Computer Science 2147, Springer 2001, ISBN 3-540-42499-7 [contents]
1990 – 1999
- 1999
- [c12]Gordon J. Brebner, Neil W. Bergmann:
Reconfigurable Computing in Remote and Harsh Environments. FPL 1999: 195-204 - [c11]Tim Kempster, Gordon J. Brebner, Peter Thanisch:
A Transactional Approach to Configuring Telecommunications Services. Databases in Telecommunications 1999: 40-53 - 1998
- [c10]Gordon J. Brebner
ECOLE: A Configurable Environment for a Local Optical Network of Workstations. CANPC 1998: 45-58 - [c9]Gordon J. Brebner
Circlets: Circuits as Applets. FCCM 1998: 300-301 - [c8]Gordon J. Brebner
Field-Programmable Logic: Catalyst for New Computing Paradigms. FPL 1998: 49-58 - [c7]Gordon J. Brebner
An Interactive Datasheet for the Xilinx XC6200. FPL 1998: 401-405 - [c6]Gordon J. Brebner, Adam Donlin:
Runtime Reconfigurable Routing. IPPS/SPDP Workshops 1998: 25-30 - 1997
- [c5]Gordon J. Brebner
The swappable logic unit: a paradigm for virtual hardware. FCCM 1997: 77-86 - [c4]Gordon J. Brebner:
Automatc identification of swappable logic units in XC6200 circuitry. FPL 1997: 173-182 - 1996
- [c3]Gordon J. Brebner:
A Virtual Hardware Operating System for the Xilinx XC6200. FPL 1996: 327-336 - 1995
- [c2]Gordon J. Brebner, John Gray:
Use of Reconfigurability in Variable-Length Code Detection at Video Rates. FPL 1995: 429-438 - 1993
- [j2]Gordon J. Brebner
A CCS-based Investigation of Deadlock in a Multi-process Electronic Mail System. Formal Aspects Comput. 5(5): 467-478 (1993) - [j1]Gordon J. Brebner
Configurable array logic circuits for computing network error detection codes. J. VLSI Signal Process. 6(2): 101-117 (1993)
1980 – 1989
- 1981
- [c1]Leslie G. Valiant, Gordon J. Brebner
Universal Schemes for Parallel Communication. STOC 1981: 263-277
Coauthor Index
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