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Baldomir Zajc
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2010 – 2019
- 2011
- [c7]Andrej Trost, Baldomir Zajc:
Logic emulators in digital systems education. EUROCON 2011: 1-4
2000 – 2009
- 2005
- [j2]Andrej Zemva, Baldomir Zajc:
Test generation for technology-specific multi-faults based on detectable perturbations. Microelectron. Reliab. 45(1): 163-173 (2005) - 2001
- [j1]Hubert Fröhlich, Andrej Koir, Baldomir Zajc:
Optimization of FPGA configurations using parallel genetic algorithm. Inf. Sci. 133(3-4): 195-219 (2001) - 2000
- [c6]Andrej Trost, Andrej Zemva, Baldomir Zajc:
Educational Programmable Hardware Prototyping and Verification System. FPL 2000: 818-821
1990 – 1999
- 1998
- [c5]Andrej Trost, Andrej Zemva, Baldomir Zajc:
Programmabel Prototyping System for Image Processing. FPL 1998: 490-494 - 1996
- [c4]Andrej Trost, Roman Kuznar, Andrej Zemva, Baldomir Zajc:
An Experimental Programmable Environment for Prototyping Digital Circuits. FPL 1996: 337-345 - 1994
- [c3]Roman Kuznar, Franc Brglez, Baldomir Zajc:
Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect. DAC 1994: 238-243 - [c2]Andrej Zemva, Franc Brglez, Krzysztof Kozminski, Baldomir Zajc:
A Functionality Fault Model: Feasibility and Applications. EDAC-ETC-EUROASIC 1994: 152-158 - [c1]Roman Kuznar, Baldomir Zajc, Franc Brglez:
A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions. EURO-DAC 1994: 271-276
Coauthor Index
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