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42nd ESSCIRC 2016: Lausanne, Switzerland
- ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, September 12-15, 2016. IEEE 2016, ISBN 978-1-5090-2972-3
- Greg Yeric:
At the core of system scaling. 1-2 - Ahmad Bahai:
Ultra-low energy systems: Analog to information. 3-6 - Tobi Delbrück:
Neuromorophic vision sensing and processing. 7-14 - Patrick Reynaert, Maarten Tytgat, Wouter Volkaerts, Alexander Standaert, Yang Zhang, Maxime De Wit
, Niels Van Thienen:
Polymer Microwave Fibers: A blend of RF, copper and optical communication. 15-20 - Gerhard P. Fettweis:
5G and the future of IoT. 21-24 - Jean-Paul Bardyn, Thierry Melly, Olivier Seller, Nicolas Sornin:
IoT: The era of LPWAN is starting now. 25-30 - Xiaolin Lu, Il Han Kim, Ariton E. Xhafa, Jianwei Zhou:
WSN for Machine Area Network applications. 31-36 - Fady Abouzeid
30% static power improvement on ARM Cortex®-A53 using static biasing-anticipation. 37-40 - Marc Pons
Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operation. 41-44 - Harsh N. Patel, Abhishek Roy, Farah B. Yahya, Ningxi Liu, Benton H. Calhoun, Kazuyuki Kumeno, Makoto Yasuda, Akihiko Harada, Taiji Ema:
A 55nm Ultra Low Leakage Deeply Depleted Channel technology optimized for energy minimization in subthreshold SRAM and logic. 45-48 - Girish Pahwa
Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approach. 49-54 - Tarun Agarwal, Iuliana P. Radu
Effect of material parameters on two-dimensional materials based TFETs: An energy-delay perspective. 55-58 - Christopher Lawrence Ayala
Experimental demonstration of a nanoelectromechanical switch-based logic library including sequential and combinational gates. 59-62 - Pankaj Sharma, Laurent Syavoch Bernard, Antonios Bazigos
Reflection amplifier based on graphene. 63-66 - Masahiro Tanaka, Kota Tsurumi, Tomoya Ishii, Ken Takeuchi:
Heterogeneously integrated program voltage generator for 1.0V operation NAND flash with best mix & match of standard CMOS process and NAND flash process. 67-70 - Syed Ahmed Aamir, Paul Müller, Andreas Hartel, Johannes Schemmel, Karlheinz Meier:
A highly tunable 65-nm CMOS LIF neuron for a large scale neuromorphic system. 71-74 - A. Ayres, Olivier Rozeau, B. Borot, Laurent Fesquet, Maud Vinet:
Delay partitioning helps reducing variability in 3DVLSI. 75-78 - Tilo Meister
20.3dB 0.39mW AM detector with single-transistor active inductor in bendable a-IGZO TFT. 79-82 - Chia-Hung Chen, Yi Zhang, Gabor C. Temes:
History, present state-of-art and future of incremental ADCs. 83-86 - Chenyu Wang, Han Jin, Yajie Qin, Li-Rong Zheng:
A wearable ECG monitoring device with flexible embedded denoising and compression. 87-90 - Wenjuan Guo, Nan Sun:
A 9.8b-ENOB 5.5fJ/step fully-passive compressive sensing SAR ADC for WSN applications. 91-94 - Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara:
Energy performance of nonvolatile power-gating SRAM using SOTB technology. 95-98 - Kazuya Masu, Daisuke Yamane, Katsuyuki Machida, Masato Sone
Development of high sensitivity CMOS-MEMS inertia sensor and its application to early-stage diagnosis of Parkinson's disease. 99-104 - Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Yasuhiro Take, Masayuki Ikebe, Tadahiro Kuroda, Masato Motomura
Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces. 105-108 - Chi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Chia-Yun Cheng, Hue-Min Lin, Chun-Chia Chen, Min-Hao Chiu, Ping Chao, Ming-Long Wu, Meng-Jye Hu, Sheng-Jen Wang, Che-Hong Chen, Shun-Hsiang Chuang, Hsiu-Yi Lin, Fu-Chun Yeh, Chia-Hung Kao, Yi-Chang Chen, Chia-Lin Ho, Yenchieh Huang, Hsiao-En Chen, Chih-Wen Yang, Hsuan-Wen Peng:
A 2.6mm2 0.19nJ/pixel VP9 and multi-standard decoder LSI for Android 4K TV applications. 109-112 - Priyanka Raina, Mehul Tikekar, Anantha P. Chandrakasan:
An energy-scalable accelerator for blind image deblurring. 113-116 - Jinmook Lee, Seongwook Park, Injoon Hong, Hoi-Jun Yoo:
An 8.3mW 1.6Msamples/s multi-modal event-driven speech enhancement processor for robust speech recognition in smart glasses. 117-120 - Shing Tak Yan, Lu Ye, Hongbing Wu, Raghavendra Kulkarni, Edward Myers, Hsieh-Chih Shih, Shadi Saberi, Darshan Kadia, Dizle Ozis, Lei Zhou, Eric Middleton, Joo Leong Tham:
An 802.11a/b/g/n/ac WLAN Transceiver for 2×2 MIMO and simultaneous dual-band operation with +29 dBm Psat integrated power amplifiers. 121-124 - Xiaoyan Wang, Johan H. C. van den Heuvel, Gert-Jan van Schaik, Chuang Lu, Yuming He, Ao Ba, Benjamin Busze, Ming Ding, Yao-Hong Liu
A 0.9-1.2V supplied, 2.4GHz Bluetooth Low Energy 4.0/4.2 and 802.15.4 transceiver SoC optimized for battery life. 125-128 - Raghavasimhan Thirunarayanan, David Ruffieux, Nicola Scolari, Christian C. Enz:
A 51.4 Mb/s FSK transmitter employing a Phase Domain Digital Synthesizer with 1.5 µs start-up for energy efficient duty cycling. 129-132 - Yashar Rajavi, Mazhareddin Taghivand, Kamal Aggarwal, Andrew Ma, Ada S. Y. Poon:
An energy harvested ultra-low power transceiver for Internet of Medical Things. 133-136 - Shih-En Chen, Kuang-Wei Cheng:
A 433 MHz 54 µW OOK/FSK/PSK compatible wake-up receiver with 11 µW low-power mode based on injection-locked oscillator. 137-140 - Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata
A 500MHz-BW -52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter. 141-144 - Ilias Sourikopoulos
A digital delay line with coarse/fine tuning through gate/body biasing in 28nm FDSOI. 145-148 - Hiroki Asano, Tetsuya Hirose, Keishi Tsubaki, Taro Miyoshi, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa:
A 1.66-nW/kHz, 32.7-kHz, 99.5ppm/°C fully integrated current-mode RC oscillator for real-time clock applications with PVT stability. 149-152 - Christian Fraisse, Angelo Nagari:
A ΣΔ sense chain using chopped integrators for ultra-low-noise MEMS system. 153-156 - Minseo Kim, Unsoo Ha, Yongsu Lee, Kyuho Jason Lee, Hoi-Jun Yoo:
A 82nW chaotic-map true random number generator based on sub-ranging SAR ADC. 157-160 - David Robertson
Data converter reflections: 19 papers from the last ten years that deserve a second look. 161-164 - Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh, Vivek Bhatia, Shivani Chaudhary, Vigyan Jain, Stéphane Le Tual, Rakesh Malik:
A 0.065mm2 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBB. 165-168 - Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin
A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction. 169-172 - Saikrishna Ganta, Alfredo Tomasini, Ajay Taparia, Taehee Cho, Mandar Kulkarni, Ozan Erdogan:
A 12 bit, 2-MS/s, 0.016-mm2 column-parallel readout cyclic ADC, having 50% reduced slew rate requirement due to feed-forward spike eliminator. 173-176 - Carsten Wulff
A compiled 3.5fJ/conv.step 9b 20MS/s SAR ADC for wireless applications in 28nm FDSOI. 177-180 - Xiao Xiao, Amanda Pratt, Ali M. Niknejad, Elad Alon, Borivoje Nikolic
A 65nm CMOS wideband TDD front-end with integrated T/R switching via PA re-use. 181-184 - Suchendranath Popuri, Vijaya Sankara Rao Pasupureddi, Johannes Sturm
A tunable gain and tunable band active balun LNA for IEEE 802.11ac WLAN receivers. 185-188 - Loai G. Salem, James F. Buckwalter, Patrick P. Mercier
A recursive house-of-cards digital power amplifier employing a λ/4-less Doherty power combiner in 65nm CMOS. 189-192 - Neelanjan Sarmah
A 200-225 GHz SiGe Power Amplifier with peak Psat of 9.6 dBm using wideband power combination. 193-196 - Dongsheng Yang, Wei Deng, Bangan Liu, Teerachot Siriburanon
An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB. 197-200 - Werner Grollitsch, Roberto Nonis:
A fractional-N, all-digital injection-locked PLL with wide tuning range digitally controlled ring oscillator and Bang-Bang phase detection for temperature tracking in 40nm CMOS. 201-204 - Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada
A 2 GHz 3.1 mW type-I digital ring-based PLL. 205-208 - Ying Wu, Mina Shahmohammadi, Yue Chen
A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise. 209-212 - Cheng-Ru Ho, Mike Shuo-Wei Chen:
Interference-induced DCO spur mitigation for digital phase locked loop in 65-nm CMOS. 213-216 - Jonas Handwerker
An array of fully-integrated quadrature TX/RX NMR field probes for MRI trajectory mapping. 217-220 - Ha Le-Thai, Adi Xhakoni, Georges G. E. Gielen:
A column-and-row-parallel CMOS image sensor with thermal and 1/f noise suppression techniques. 221-224 - Hossein Kassiri, Gairik Dutta, Nima Soltani, Chang Liu, Yu Hu, Roman Genov:
An impedance-tracking battery-less arbitrary-waveform neurostimulator with load-adaptive 20V voltage compliance. 225-228 - Eric P. Pepin, John P. Uehlin, Daniel Micheletti, Steve I. Perlmutter
A high-voltage compliant, electrode-invariant neural stimulator front-end in 65nm bulk-CMOS. 229-232 - Erik J. Peterson, David A. Dinsmoor, Dustin J. Tyler
Stimulation artifact rejection in closed-loop, distributed neural interfaces. 233-236 - Neelakantan Narasimman, Tony T. Kim:
A 0.3 V, 49 fJ/conv.-step VCO-based delta sigma modulator with self-compensated current reference for variation tolerance. 237-240 - Shaolan Li, Nan Sun:
A 174.3dB FoM VCO-based CT ΔΣ modulator with a fully digital phase extended quantizer and tri-level resistor DAC in 130nm CMOS. 241-244 - Marco Grassi
A multi-mode SC audio ΣΔ Modulator for MEMS microphones with reconfigurable power consumption, noise-shaping order, and DR. 245-248 - Zhijie Chen, Masaya Miyahara, Akira Matsuzawa:
A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder. 249-252 - Tohru Kaneko, Yuya Kimura, Koji Hirose, Masaya Miyahara, Akira Matsuzawa:
A 76-dB-DR 6.8-mW 20-MHz bandwidth CT ΔΣ ADC with a high-linearity Gm-C filter. 253-256 - Hans Reyserhove
A 16.07pJ/cycle 31MHz fully differential transmission gate logic ARM Cortex M0 core in 40nm CMOS. 257-260 - Jeremy Constantin, Andrea Bonetti, Adam Teman
DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment. 261-264 - Kan Takeuchi, Masaki Shimada, Takeshi Okagaki, Koji Shibutani, Koji Nii, Fumio Tsuchiya:
FEOL/BEOL wear-out estimator using stress-to-frequency conversion of voltage/temperature-sensitive ring oscillators for 28nm automotive MCUs. 265-268 - Ben Keller, Martin Cochet, Brian Zimmer, Yunsup Lee, Milovan Blagojevic, Jaehwa Kwak, Alberto Puggelli, Stevo Bailey, Pi-Feng Chiu, Daniel Palmer Dabbelt, Colin Schmidt, Elad Alon, Krste Asanovic, Borivoje Nikolic
Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC. 269-272 - Jan Cools
A 40nm bulk CMOS line driver for broadband communication. 273-276 - Valentijn De Smedt
A 650 V, 3 A three-phase fully-integrated BLDC motor driver with charge pump and level shifters. 277-280 - R. J. E. Jansen, Scott Lindner:
High-voltage tolerant bi-state self-biasing output driver using cascade complementary latches in twin-well CMOS technology. 281-284 - Andrea Barbieri, Sergio Pernici:
A Differential Difference Amplifier with Dynamic Resistive Degeneration for MEMS microphones. 285-288 - Alessandra Pipino, Marcello De Matteis, Alessandro Pezzotta, Federica Resta
A 22.5MHz 21.5dBm-IIP3 4th-Order FLFB analog filter. 289-292 - Sang-Hoon Kim, Hoon Shin, Youngkyun Jeong, June-Hee Lee, Jaehyuk Choi, Jung-Hoon Chun:
A 12-Gb/s dual-channel transceiver for CMOS image sensor systems. 293-296 - Marc Erett, James Hudner, Declan Carey, Ronan Casey, Kevin Geary, Kay Hearne, Pedro Neto, Thomas Mallard, Vikas Sooden, Mark Smyth, Yohan Frans, Jay Im, Parag Upadhyaya, Wenfeng Zhang, Winson Lin, Bruce Xu, Ken Chang:
A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET. 297-300 - Tetsuya Iizuka, Norihito Tohge, Satoshi Miura, Yoshimichi Murakami, Toru Nakura, Kunihiro Asada:
A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking. 301-304 - Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao
A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS. 305-308 - Hazar Yueksel, Matthias Braendli
A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS. 309-312 - Nachiket V. Desai, Anantha P. Chandrakasan:
A ZVS resonant receiver with maximum efficiency tracking for device-to-device wireless charging. 313-316 - Saad Bin Nasir
A 130nm hybrid low dropout regulator based on switched mode control for digital load circuits. 317-320 - Samantak Gangopadhyay, Saad Bin Nasir
UVFR: A Unified Voltage and Frequency Regulator with 500MHz/0.84V to 100KHz/0.27V operating range, 99.4% current efficiency and 27% supply guardband reduction. 321-324 - Alexis Schindler, Benno Koeppl, Ansgar Pottbaecker, Markus Zannoth, Bernhard Wicht
Gate driver with 10 / 15ns in-transition variable drive current and 60% reduced current dip. 325-328 - Salvatore Levantino
Bang-bang digital PLLs. 329-334 - Gabriele Anzalone, Enrico Monaco, Guido Albasini, Simone Erba, Andrea Mazzanti:
A 0.2-11.7GHz, high accuracy injection-locking multi-phase generation with mixed analog/digital calibration loops in 28nm FDSOI CMOS. 335-338 - Abhirup Lahiri, Nitin Gupta:
A 0.0175mm2 600µW 32kHz input 307MHz output PLL with 190psrms jitter in 28nm FD-SOI. 339-342 - Markus Scholl, Ye Zhang, Ralf Wunderlich, Stefan Heinen:
A 80 nW, 32 kHz charge-pump based ultra low power oscillator with temperature compensation. 343-346 - Wei-Zen Chen, Po-I Kuo:
A ΔΣ TDC with sub-ps resolution for PLL built-in phase noise measurement. 347-350 - Michael Kalcher
Self-aligned open-loop local quadrature phase generator. 351-354 - Hundo Shin, Ramesh Harjani:
A 1GHz signal bandwidth 4-channel-I/Q polyphase-FFT filter bank. 355-358 - Qingrui Meng, Ramesh Harjani:
An easily extendable FFT based four-channel, four-beam receiver with progressive partial spatial filtering in 65nm. 359-362 - Fabio Padovan, Marc Tiebout, Andrea Neviani
A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers. 363-366 - Hamidreza Aghasi
Design of broadband mm-wave and THz frequency doublers. 367-372 - Lorenzo Iotti, Andrea Mazzanti, Francesco Svelto:
A multi-core VCO and a frequency quadrupler for E-Band adaptive-modulation links in 55nm BiCMOS. 373-376 - Ruixin Wang, Fa Foster Dai:
A 1∼1.5 GHz capacitive coupled inductor-less multi-ring oscillator with improved phase noise. 377-380 - M. Houdebine, Emmanuel Chataigner, R. Boulestin, C. Grundrich, Davy Thevenet, Sébastien Pruvost, H. Sherry, F. Colmagro, F. Bailleul, Sébastien Dedieu:
An 85-GHz fully integrated all digital fractional frequency synthesizer for e-band backhaul and radar applications in 55-nm BiCMOS. 381-384 - Arindam Sanyal, Nan Sun:
A 55fJ/conv-step hybrid SAR-VCO ΔΣ capacitance-to-digital converter in 40nm CMOS. 385-388 - J. P. Sanjurjo, Enrique Prefasi
An energy-efficient 17-bit noise-shaping Dual-Slope Capacitance-to-Digital Converter for MEMS sensors. 389-392 - Marco Crescentini, Michele Biondi, Marco Bennati, P. Alberti, Giulia Luciani, Cinzia Tamburini, Matteo Pizzotti
A 2 MS/s 10A Hall current sensor SoC with digital compressive sensing encoder in 0.16 µm BCD. 393-396 - Junfeng Jiang, Kofi A. A. Makinwa:
A hybrid multi-path CMOS magnetic sensor with 76 ppm/°C sensitivity drift. 397-400 - Muhammad Ali, Matteo Perenzoni, David Stoppa:
A high-gain, low-noise switched capacitor readout for FET-based THz detectors. 401-404 - Wenjuan Guo, Nan Sun:
A 12b-ENOB 61µW noise-shaping SAR ADC with a passive integrator. 405-408 - Maoqiang Liu, Arthur H. M. van Roermund, Pieter Harpe:
A 7.1fJ/conv.-step 88dB-SFDR 12b SAR ADC with energy-efficient swap-to-reset. 409-412 - Xiyuan Tang, Long Chen, Jeonggoo Song, Nan Sun:
A 10-b 750µW 200MS/s fully dynamic single-channel SAR ADC in 40nm CMOS. 413-416 - Kareem Ragab, Nan Sun:
A 1.4mW 8b 350MS/s loop-unrolled SAR ADC with background offset calibration in 40nm CMOS. 417-420 - Dante Gabriel Muratore
An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology. 421-424 - Teng Yang, Peter R. Kinget
Register file circuits and post-deployment framework to monitor aging effects in field. 425-428 - Babak Mohammadi, Oskar Andersson
A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI. 429-432 - Avishek Biswas, Anantha P. Chandrakasan:
A 0.36V 128Kb 6T SRAM with energy-efficient dynamic body-biasing and output data prediction in 28nm FDSOI. 433-436 - Zhao Chuan Lee, M. Sultan M. Siddiqui, Zhi-Hui Kong, Tony Tae-Hyoung Kim:
An 8T SRAM with BTI-Aware Stability Monitor and two-phase write operation for cell stability improvement in 28-nm FDSOI. 437-440 - Junmin Jiang
A digitally-controlled 2-/3-phase 6-ratio switched- capacitor DC-DC converter with adaptive ripple reduction and efficiency improvements. 441-444 - Nicolas Butzen
MIMO Switched-Capacitor converter using only parasitic capacitance with Scalable Parasitic Charge Redistribution. 445-448 - Daniel Lutz
A 120/230 Vrms-to-3.3V micro power supply with a fully integrated 17V SC DCDC converter. 449-452 - Monodeep Kar, Arvind Singh, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
An integrated inductive VR with a 250MHz all-digital multisampled compensator and on-chip auto-tuning of coefficients in 130nm CMOS. 453-456 - Enkhbayasgalan Gantsog, Deyu Liu, Alyssa B. Apsel:
0.89 mW on-chip jitter-measurement circuit for high speed clock with sub-picosecond resolution. 457-460 - Kwanyeob Chae, JongRyun Choi, Shinyoung Yi, Won Lee, Sanghoon Joo, Hyunhyuck Kim, Hyungkwon Yi, Yoonjee Nam, Jinho Choi, Sanghune Park, Sanghyun Lee:
A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technology. 461-464 - Vincent Camus
Approximate 32-bit floating-point unit design with 53% power-area product reduction. 465-468 - So Hasegawa, Junichiro Kadomoto, Atsutake Kosuge, Tadahiro Kuroda:
A 1 Tb/s/mm2 inductive-coupling side-by-side chip link. 469-472 - Nathaniel Ross Pinckney, Dennis Sylvester, David T. Blaauw:
Supply boosting for high-performance processors in flip-chip packages. 473-476 - Thomas Toifl, Matthias Braendli
Design considerations for 50G+ backplane links. 477-482 - Niels Van Thienen, Yang Zhang, Maxime De Wit
An 18Gbps polymer microwave fiber (PMF) communication link in 40nm CMOS. 483-486 - Mohamed Hussein Eissa, Ahmed Awny, Georg Winzer, Marcel Kroh, Stefan Lischke, Dieter Knoll, Lars Zimmermann, Dietmar Kissinger, Ahmet Cagri Ulusoy:
A wideband monolithically integrated photonic receiver in 0.25-µm SiGe: C BiCMOS technology. 487-490 - Nandish Mehta
A 12Gb/s, 8.6µApp input sensitivity, monolithic-integrated fully differential optical receiver in CMOS 45nm SOI process. 491-494 - Milad Ataei, Alexis Boegli, Pierre-André Farine:
Phase and frequency self-configurable efficient low voltage harvester for zero power wearable devices. 495-498 - Sung-Youb Jung, Myeong-Jae Park, Minbok Lee, Joonseok Yang, Jaeha Kim:
Time slot optimization algorithm for multisource energy harvesting systems. 499-502 - Karim Rawy, Felix Kalathiparambil George, Dominic Maurath, Tony T. Kim:
A time-based self-adaptive energy-harvesting MPPT with 5.1-µW power consumption and a wide tracking range of 10-µA to 1-mA. 503-506 - Khondker Zakir Ahmed, Mohammad Faisal Amir, Jong Hwan Ko, Saibal Mukhopadhyay:
Reconfigurable 96×128 active pixel sensor with 2.1µW/mm2 power generation and regulated multi-domain power delivery for self-powered imaging. 507-510
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