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Fady Abouzeid
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2020 – today
- 2024
- [j5]Juan Suzano
, Fady Abouzeid
On Hardware Security and Trust for Chiplet-Based 2.5D and 3D ICs: Challenges and Innovations. IEEE Access 12: 29778-29794 (2024) - [c20]Juan Suzano, Antoine Chastand, Emanuele Valea, Giorgio Di Natale, Anthony Philippe, Fady Abouzeid, Philippe Roche:
IEEE 1838 compliant scan encryption and integrity for 2.5/3D ICs. ETS 2024: 1-6 - 2021
- [c19]Sébastien Thomet, Serge De Paoli, Jean-Marc Daveau, Valérie Bertin, Fady Abouzeid
FIRECAP: Fail-Reason Capturing hardware module for a RISC-V based System on a Chip. DFT 2021: 1-6
2010 – 2019
- 2018
- [j4]Guenole Lallement
A 2.7 pJ/cycle 16 MHz, 0.7 µW Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI. IEEE J. Solid State Circuits 53(7): 2088-2100 (2018) - [c18]Guenole Lallement, Fady Abouzeid
A 140 nW, 32.768 kHz, 1.9 ppm/°C Leakage-Based Digitally Relocked Clock Reference with 0.1 ppm Long-Term Stability in 28nm FD-SOI. A-SSCC 2018: 197-200 - [c17]Yvan Debizet, Guénolé Lallement, Fady Abouzeid
Q-Learning-based Adaptive Power Management for IoT System-on-Chips with Embedded Power States. ISCAS 2018: 1-5 - 2017
- [c16]Martin Cochet, Sylvain Clerc, Guenole Lallement, Fady Abouzeid
A 0.40pJ/cycle 981 μm2 voltage scalable digital frequency generator for SoC clocking. A-SSCC 2017: 69-72 - [c15]Guenole Lallement, Fady Abouzeid
A 2.7pJ/cycle 16MHz SoC with 4.3nW power-off ARM Cortex-M0+ core in 28nm FD-SOI. ESSCIRC 2017: 153-162 - 2016
- [c14]Davide Rossi
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. COOL Chips 2016: 1-3 - [c13]Fady Abouzeid
30% static power improvement on ARM Cortex®-A53 using static biasing-anticipation. ESSCIRC 2016: 37-40 - 2015
- [j3]Edith Beigné
A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. IEEE J. Solid State Circuits 50(1): 125-136 (2015) - [c12]Fady Abouzeid
28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors. ESSCIRC 2015: 108-111 - [c11]Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Gilles Gasiot, Fady Abouzeid
Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test. IRPS 2015: 12 - [c10]Sylvain Clerc, Fady Abouzeid
Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. ISQED 2015: 366-370 - [c9]Sylvain Clerc, Mehdi Saligane, Fady Abouzeid
8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. ISSCC 2015: 1-3 - 2014
- [j2]Fady Abouzeid
Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI. IEEE J. Solid State Circuits 49(7): 1499-1505 (2014) - [c8]Robin Wilson, Edith Beigné
27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. ISSCC 2014: 452-453 - 2013
- [c7]Edith Beigné, Alexandre Valentian, Bastien Giraud, Olivier Thomas, Thomas Benoist, Yvain Thonnart, Serge Bernard, Guillaume Moritz, Olivier Billoint, Y. Maneglia, Philippe Flatresse, Jean-Philippe Noel, Fady Abouzeid
Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. DATE 2013: 613-618 - [c6]Fady Abouzeid
Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI. ESSCIRC 2013: 205-208 - 2012
- [c5]Fady Abouzeid
28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V, 10MHz/700MHz, 252bits frame error-decoder. ESSCIRC 2012: 153-156 - [c4]Sylvain Clerc, Fady Abouzeid
A 65nm SRAM achieving 250mV retention and 350mV, 1MHz, 55fJ/bit access energy, with bit-interleaved radiation Soft Error tolerance. ESSCIRC 2012: 313-316 - [c3]Sylvain Clerc, Fady Abouzeid
A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance. ICICDT 2012: 1-4 - 2011
- [j1]Fady Abouzeid
40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications. ACM Trans. Design Autom. Electr. Syst. 16(3): 35:1-35:17 (2011) - [c2]Sylvain Clerc, Fady Abouzeid
A 240mV 1MHz, 340mV 10MHz, 40nm CMOS, 252 bits frame decoder using ultra-low voltage circuit design platform. ICECS 2011: 117-120
2000 – 2009
- 2009
- [c1]Fady Abouzeid
A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications. ISLPED 2009: 225-230
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