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Marc-Nicolas Morgan
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2010 – 2019
- 2016
- [c5]Marc Pons
, Thanh-Chau Le, Claude Arm, Daniel Séverac, Jean-Luc Nagel, Marc-Nicolas Morgan, Stéphane Emery
Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operation. ESSCIRC 2016: 41-44 - 2013
- [c4]Marc Pons
Ultra low-power standard cell design using planar bulk CMOS in subthreshold operation. PATMOS 2013: 9-15 - 2012
- [c3]Marc Pons
Fixed origin corner square inspection layout regularity metric. DATE 2012: 1397-1402 - [c2]Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hübner, Jürgen Becker, Sébastien Pillement
Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures. ICSAMOS 2012: 228-235 - 2010
- [c1]Erwan Le Roux, Nicola Scolari, Budhaditya Banerjee, Claude Arm, Patrick Volet, Daniel Sigg, Pascal Heim, Jean-Félix Perotto, François Kaess, Nicolas Raemy, Alexandre Vouilloz, David Ruffieux, Matteo Contaldo, Frédéric Giroud, Daniel Séverac, Marc-Nicolas Morgan, Steve Gyger, Cedric Monneron, Thanh-Chau Le, Cesar Henzelin, Vincent Peiris:
A 1V RF SoC with an 863-to-928MHz 400kb/s radio and a 32b Dual-MAC DSP core for Wireless Sensor and Body Networks. ISSCC 2010: 464-465
2000 – 2009
- 2009
- [j2]Claude Arm, Steve Gyger, Jean-Marc Masgonty, Marc-Nicolas Morgan, Jean-Luc Nagel, Christian Piguet, Flavio Rampogna, Patrick Volet:
Low-Power 32-bit Dual-MAC 120 µW/MHz 1.0 V icyflex1 DSP/MCU Core. IEEE J. Solid State Circuits 44(7): 2055-2064 (2009) - 2008
- [j1]Christian Piguet, Jean-Luc Nagel, Vincent Peiris, Steve Gyger, Daniel Séverac, Marc-Nicolas Morgan, Jean-Marc Masgonty:
Low-Power Heterogeneous Systems-on-Chips. J. Low Power Electron. 4(2): 111-126 (2008)
Coauthor Index
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