default search action
APCCAS 2020: Ha Long, Vietnam
- 2020 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020, Ha Long, Vietnam, December 8-10, 2020. IEEE 2020, ISBN 978-1-7281-9396-0
- Ren Ping Liu:
IoT and Blockchain: Technologies, Challenges, and Applications. i - Bah-Hwee Gwee:
Hardware Attack and Assurance with Machine Learning: A Security Threat to Circuits and Systems. i - Yimin Wu, Jingchao Lan, Min Chen, Fan Ye, Junyan Ren:
A 16-channel 50MS/s 14bit Pipelined-SAR ADC for Integrated Ultrasound Imaging Systems. 3-6 - Yimin Wu, Shuai Li, Longheng Luo, Fan Ye, Junyan Ren:
An Area-Power-Efficient AFE with NS-SAR ADC For High-Frequency Ultrasound Applications. 7-10 - Zhechong Lan, Li Dong, Xixin Jing, Liheng Liu, Ken Li, Ziyan Shen, Zhiming Li, Li Geng:
A Two-step SAR ADC with Synchronous DEM Calibration Achieving Up to 15% Power Reduction. 11-14 - Thinh Tran-Dinh, Hieu Minh Pham
, Bac Phuong Dao, Hien Hoang-Thi, Loan Pham-Nguyen
Low-Power PMIC with Two Hybrid Converters for TEG Application. 15-18 - Tieu-Khanh Luong, Hong-Hanh Hoang, Hoang-Anh Nguyen-Minh, Cong Dang Bui, Son Bui, Trung-Kien Nguyen:
A Spur-Free Low-Complexity Hybrid Nested Bus-Splitting/SP-MASH Digital Delta-Sigma Modulator. 19-22 - Ting Wang, Tsung-Te Liu:
ECC processor over the Koblitz curves with τ-NAF Converter and Square-Square-Add Algorithm. 23-26 - Liulu He, Xiaoru Xie, Jun Lin, Zhongfeng Wang:
Efficient FPGA design for Convolutions in CNN based on FFT-pruning. 27-30 - Kentaro Nagai, Jun Shiomi, Hidetoshi Onodera:
A DLL-based Body Bias Generator for Minimum Energy Operation with Independent P-well and N-well Bias. 31-34 - Ngo-Doanh Nguyen
A Lightweight AEAD encryption core to secure IoT applications. 35-38 - Ziwei Li
A Low-Power Low-Noise Dynamic Comparator With Latch-Embedding Floating Amplifier. 39-42 - Hua Fan, Xinjie Wu, Quanyuan Feng, Ke Zhang, Jia Zhang:
Capacitive recombination calibration method to improve the performance of SAR ADC. 43-46 - Xianglong Bai
A Single-Stage Delay-Tuned Active Rectifier for Constant-Current Constant-Voltage Wireless Charging. 47-49 - Jitendra Kumar Mishra, Prasanna Kumar Misra, Manish Goswami:
Design of SRAM cell using Voltage Lowering and Stacking Techniques for Low Power Applications. 50-53 - Yuka Nakamatsu, Takao Kihara:
Dynamic Reduction of Power Consumption in Direct-RF Sampling Receivers with Variable Decimation. 54-57 - Van-Toan Nguyen, Viet-Son Bui, Trung-Kien Nguyen:
High-Performance Implementation of Adaptive IQ Mismatch Compensator in Direct-Conversion Transceiver. 58-61 - Zaiyong Liu, Hai-Bao Chen, Tianshu Hou:
Stress Evolution Analysis of EM-Induced Void Growth for Multi-Segment Interconnect Wires. 62-65 - Ngoc-Tuan Do
Performance Analysis of Non-Profiled Side Channel Attacks Based on Convolutional Neural Networks. 66-69 - Yuxuan Du, Xinchao Shang, Weiwei Shan:
An Energy-Efficient Time-Domain Binary Neural Network Accelerator with Error-Detection in 28nm CMOS. 70-73 - Pham-Khoi Dong, Hung K. Nguyen, Van-Phuc Hoang
Low-Power Implementation of a High-Throughput Multi-core AES Encryption Architecture. 74-77 - Yeqing Wang, Zhouchen Ma, Yan Liu, Jian Zhao, Lei Zhang, Zongmin Wang:
Sub-Sampling Phase-Locked Loop with Ultra-mini Dead Zone For Locking Time Reduction. 78-81 - Wenbin He, Ziwei Li
A Low Power Reference Voltage Buffer and High Density Unit capacitor in a 12b 200MS/s SAR ADC. 82-85 - Alex Marionne A. del Castillo, Ramon G. Garcia, Febus Reidj G. Cruz:
Open Top Socketed Evaluation Board for Bench Test and Fault Localization on GaAs RF Device. 86-89 - Gaofeng Tan, Haolin Lu, Xinyu Qin, Jiliang Zhang, Jingying Zhang, Yan Liu, Liang Qi:
A Self-coupled DT MASH ΔΣ Modulator with High Tolerance to Noise Leakage. 90-93 - Hua Fan, Xiaohu Qi, Quanyuan Feng:
"Truth from Practice, Learning beyond Teaching" Exploration in Teaching Analog Integrated Circuit. 94-97 - Chua-Chin Wang, Shao-Wei Lu:
100 MHz Random Number Generator Design Using Interleaved Metastable NAND/NOR Latches*. 98-101 - Xinchao Zhong, Chiu-Wing Sham
A RISC-V SoC for Mobile Payment Based on Visible Light Communication. 102-105 - Antonello Florio
Digital Phase Estimation through an I/Q Approach for Angle of Arrival Full-Hardware Localization. 106-109 - Matthew Brown, Carlos E. Saavedra:
Frequency-Tunable Quasi-Elliptic Filter Using Liquid Metal. 110-113 - Kohei Koike, Kenta Suzuki, Mengnan Ke, Kenjiro Mori, Takumi Ito, Takayuki Kawahara:
Damage-Position Identification of Wooden-House Models for Structural Health Monitoring Using Machine Learning. 114-117 - Yuya Maekawa, Syuya Nakagawa, Hiroki Ishikuro:
A Highly Linear Amp-Less Interface Circuit for Capacitive Sensors with ΔΣ C-DAC. 118-120 - Jinghao Ye, Masao Yanagisawa, Youhua Shi:
A High-Performance Symmetric Hybrid Form Design for High-Order FIR Filters. 121-124 - Sarmad Ozan
Low-Noise Amplifier with Wideband Feedforward Linearisation for Mid-Band 5G Receivers. 125-128 - Celal Erbay
Random Number Generator Based on Miniature Microbial Fuel Cells. 129-132 - Xuemei Fan, Hongwei Li, Qiang Li, Rujin Wang, Hao Liu, Shengli Lu:
A Light-Weight Timing Resilient Scheme for Near-Threshold Efficient Digital ICs. 133-136 - Danyang Zhu, Yifeng Song, Jing Tian, Zhongfeng Wang, Haobo Yu:
An Efficient Accelerator of the Squaring for the Verifiable Delay Function Over a Class Group. 137-140 - Xiao Hu, Jing Tian, Zhongfeng Wang:
Fast Permutation Architecture on Encrypted Data for Secure Neural Network Inference. 141-144 - Chua-Chin Wang, Chia-Yi Huang, Chu-Han Lin, Chia-Hung Yeh, Guan-Xian Liu, Yu-Cheng Chou:
3D-Modeling Dataset Augmentation for Underwater AUV Real-time Manipulations. 145-148 - Hongyu Gu, Zhecheng Yang, Hong Chen:
Automatic Tongue Image Segmentation Based on Thresholding and an Improved Level Set Model. 149-152 - Ha Thi Bui, Chinh Doan Tran
Design and manufacture power pre-amplifier module for transmitter of ground station at S-band. 153-156 - Yen-Bor Lin, Chih-Chieh Ma, Chong-Cheng Hsu, Ting-Chia Ou, Tsung-Chieh Cheng, Wen-Fu Chen:
An Energy Operating System Adaptive for The Sustainable And Green Energy. 157-160 - Weng-Geng Ho, Chuan-Seng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Bah-Hwee Gwee:
High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC. 161-164 - Jiayu Wen, Yufei Ma, Zhongfeng Wang:
An Efficient FPGA Accelerator Optimized for High Throughput Sparse CNN Inference. 165-168 - Marcus Miguel V. Vicedo, Febus Reidj G. Cruz, Ramon G. Garcia:
Copper Coin Over Thermal VIA in PCB for Thermal Management of 12W. 169-172 - Tee Hui Teo
Fast Object Detection on the Road. 173-176 - Heng-Sheng Lin, Jian-Jiun Ding, Jin-Yu Huang:
Graph Saliency Network: Using Graph Convolution Network on Saliency Detection. 177-180 - Ji-Ting Wu, Jian-Jiun Ding:
Improved Angle Freeman Chain Code Using Improved Adaptive Arithmetic Coding. 181-184 - Bo-Shue Lin, Ding-Wen Hsu, Chin-Han Shen, Hsu-Feng Hsiao:
Using Fully Connected and Convolutional Net for GAN-Based Face Swapping. 185-188 - Nguyen Thanh Trung, Dinh Hoan Trinh, Nguyen Linh Trung, Tran Thi Thuy Quynh, Manh-Ha Luu:
Dilated Residual Convolutional Neural Networks for Low-Dose CT Image Denoising. 189-192 - Chia-Heng Lee, Ying-Tuan Hsu
Design of an 45nm NCFET Based Compute-in-SRAM for Energy-Efficient Machine Learning Applications. 193-196 - Kenta Suzuki, Takumi Ito, Kohei Koike, Takayuki Kawahara, Mengnan Ke, Kenjiro Mori:
Improvement of Generalization Performance for Timber Health Monitoring using Machine Learning. 197-200 - Chao Ni
LBFP: Logarithmic Block Floating Point Arithmetic for Deep Neural Networks. 201-204 - Min Chen, Yimin Wu, Jingchao Lan, Fan Ye, Chixiao Chen, Junyan Ren:
A Calibration Scheme for Nonlinearity of the SAR-Pipelined ADCs Based on a Shared Neural Network. 205-208 - Duy-Anh Nguyen, Xuan-Tu Tran, Khanh N. Dang, Francesca Iacopi:
A lightweight Max-Pooling method and architecture for Deep Spiking Convolutional Neural Networks. 209-212 - Lu Lu, Ju Eon Kim, Vishal Sharma, Tony Tae-Hyoung Kim:
ReRAM Device and Circuit Co-Design Challenges in Nano-scale CMOS Technology. 213-216 - Yi-Hong Chen, Yan-Ting Liu, Tsun-Kuang Chi, Chiung-An Chen, Yih-Shyh Chiou, Ting-Lan Lin, Shih-Lun Chen:
Lossless EEG Compression Algorithm Based on Semi-Supervised Learning for VLSI Implementation. 217-219 - Guowei Chen, Cong Dang Bui, Xinyang Yu, Md. Zahidul Islam
A 72-nW 440-mV Time Register Using Stacked-NMOS-Switched Gated Delay Cell in Biomedical Applications. 220-223 - Salih Ergün
Random Number Generator Based on Skew-tent Map and Chaotic Sampling. 224-227 - Burak Acar, Tufan Coskun Karalar:
Experimental Cryptanalysis of No-equilibrium Chaotic System Based Random Number Generator. 228-231 - Sathwik GS, Barun Kumar Acharya, Bilal Ali, Deepu S. P., David S. Sumam:
Real-Time Hardware Implementation of 3D Sound Synthesis. 232-235 - Vannhu Le, MinhNghia Pham, Vandang Hoang:
Axial Resolution Enhacement of Light-Sheet Microscopy via two Light-Sheets. 236-239 - Jianglin Wei
Revisit to Floating-Point Division Algorithm Based on Taylor-Series Expansion. 240-243 - Chien-Cheng Tseng, Su-Ling Lee:
Missing Temperature Data Recovery Methods Based on Smoothness, Bandlimitedness and Sparseness Priors. 244-247 - Xianfeng Tang, Peining Zhen, Ming Kang, Hang Yi, Wei Wang, Hai-Bao Chen:
Learning Enriched Features for Video Denoising with Convolutional Neural Network. 248-251 - Ling Zhang, Wei Zhou, Jingwei Li, Juan Li, Xin Lou:
Histogram of Oriented Gradients Feature Extraction Without Normalization. 252-255
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-27 20:16 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: