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Jing Tian 0004
Person information
- affiliation: Nanjing University, School of Electronic Science and Engineering, China
Other persons with the same name
- Jing Tian — disambiguation page
- Jing Tian 0001 — Queen Mary University of London, UK
- Jing Tian 0002
— National University of Singapore, Institute of Systems Science, Singapore (and 3 more)
- Jing Tian 0003
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2020 – today
- 2024
- [i7]Jing Tian, Bo Wu, Lang Feng, Haochen Zhang, Zhongfeng Wang:
A Fast and Efficient SIKE Co-Design: Coarse-Grained Reconfigurable Accelerators with Custom RISC-V Microcontroller on FPGA. IACR Cryptol. ePrint Arch. 2024: 1120 (2024) - 2023
- [j16]Danyang Zhu
Low-latency Hardware Architecture for VDF Evaluation in Class Groups. IEEE Trans. Computers 72(6): 1706-1717 (2023) - [j15]Minghao Li
Reconfigurable and High-Efficiency Polynomial Multiplication Accelerator for CRYSTALS-Kyber. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8): 2540-2551 (2023) - [j14]Yifeng Song
A High-Speed FPGA-Based Hardware Implementation for Leighton-Micali Signature. IEEE Trans. Circuits Syst. I Regul. Pap. 70(1): 241-252 (2023) - [j13]Xiao Hu
AC-PM: An Area-Efficient and Configurable Polynomial Multiplier for Lattice Based Cryptography. IEEE Trans. Circuits Syst. I Regul. Pap. 70(2): 719-732 (2023) - [j12]Lun Ou
Fast Hardware Implementation for Extended GCD of Large Numbers in Redundant Representation. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 3094-3098 (2023) - [j11]Danyang Zhu, Rongrong Zhang, Lun Ou, Jing Tian, Zhongfeng Wang:
Low-Latency Design and Implementation of the Squaring in Class Groups for Verifiable Delay Function Using Redundant Representation. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2023(1): 438-462 (2023) - [c20]Huiyang Xiong, Bohang Xiong, Wenhao Wang, Jing Tian, Hao Zhu, Zhongfeng Wang:
Efficient FPGA-Based Accelerator of the L-BFGS Algorithm for IoT Applications. ISCAS 2023: 1-5 - [c19]Yueqin Dai, Yifeng Song, Jing Tian, Zhongfeng Wang:
High-Throughput Hardware Implementation for Haraka in SPHINCS+. ISQED 2023: 1-6 - [c18]Xinyuan Qiao
Efficient Decryption Architecture for Classic McEliece. ISQED 2023: 1-7 - [c17]Chen Li, Suwen Song, Jing Tian, Zhongfeng Wang, Çetin Kaya Koç:
An Efficient Hardware Design for Fast Implementation of HQC. SOCC 2023: 1-6 - 2022
- [j10]Jing Tian
Efficient Software Implementation of the SIKE Protocol Using a New Data Representation. IEEE Trans. Computers 71(3): 670-683 (2022) - [j9]Xiao Hu
Efficient Homomorphic Convolution Designs on FPGA for Secure Inference. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1691-1704 (2022) - [c16]Minghao Li, Jing Tian, Xiao Hu, Yuan Cao, Zhongfeng Wang:
High-Speed and Low-Complexity Modular Reduction Design for CRYSTALS-Kyber. APCCAS 2022: 1-5 - [c15]Bohang Xiong, Jing Tian, Zhongfeng Wang:
A High-Speed Codec Architecture for Lagrange Coded Computing. ISCAS 2022: 2811-2815 - [c14]Lei Yang, Jing Tian, Bo Wu, Zhongfeng Wang, Hao Ren:
An RS-BCH Concatenated FEC Code for Beyond 400 Gb/s Networking. ISVLSI 2022: 212-216 - [c13]Samira Carolina Oliva Madrigal
Reduction-Free Multiplication for Finite Fields and Polynomial Rings. WAIFI 2022: 53-78 - [i6]Danyang Zhu, Jing Tian, Minghao Li, Zhongfeng Wang:
Low-latency Hardware Architecture for VDF Evaluation in Class Groups. IACR Cryptol. ePrint Arch. 2022: 755 (2022) - 2021
- [j8]Suwen Song
An Improved Reliability-Based Decoding Algorithm for NB-LDPC Codes. IEEE Commun. Lett. 25(4): 1153-1157 (2021) - [j7]Jing Tian
High-Speed FPGA Implementation of SIKE Based on an Ultra-Low-Latency Modular Multiplier. IEEE Trans. Circuits Syst. I Regul. Pap. 68(9): 3719-3731 (2021) - [j6]Jing Tian
Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography. IEEE Trans. Very Large Scale Integr. Syst. 29(2): 359-371 (2021) - [c12]Xiao Hu, Minghao Li, Jing Tian, Zhongfeng Wang:
DARM: A Low-Complexity and Fast Modular Multiplier for Lattice-Based Cryptography. ASAP 2021: 175-178 - [c11]Yifeng Song, Xiao Hu, Wenhao Wang, Jing Tian, Zhongfeng Wang:
High-Speed and Scalable FPGA Implementation of the Key Generation for the Leighton-Micali Signature Protocol. ISCAS 2021: 1-5 - [c10]Danyang Zhu, Jing Tian, Zhongfeng Wang:
Low-Latency Architecture for the Parallel Extended GCD Algorithm of Large Numbers. ISCAS 2021: 1-5 - [i5]Yifeng Song, Danyang Zhu, Jing Tian, Zhongfeng Wang:
A High-Speed Architecture for the Reduction in VDF Based on a Class Group. IACR Cryptol. ePrint Arch. 2021: 949 (2021) - 2020
- [j5]Jing Tian
Optimized Trellis-Based Min-Max Decoder for NB-LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs 67-II(1): 57-61 (2020) - [j4]Suwen Song
A Novel Iterative Reliability-Based Majority-Logic Decoder for NB-LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs 67-II(8): 1399-1403 (2020) - [c9]Danyang Zhu, Yifeng Song, Jing Tian, Zhongfeng Wang, Haobo Yu:
An Efficient Accelerator of the Squaring for the Verifiable Delay Function Over a Class Group. APCCAS 2020: 137-140 - [c8]Xiao Hu, Jing Tian, Zhongfeng Wang:
Fast Permutation Architecture on Encrypted Data for Secure Neural Network Inference. APCCAS 2020: 141-144 - [c7]Bo Wu, Jing Tian, Xiao Hu, Zhongfeng Wang:
A Novel Modular Multiplier for Isogeny-Based Post-Quantum Cryptography. ISVLSI 2020: 334-339 - [c6]Yifeng Song, Danyang Zhu, Jing Tian, Zhongfeng Wang:
A High-Speed Architecture for the Reduction in VDF Based on a Class Group. SoCC 2020: 147-152 - [i4]Jing Tian, Jun Lin, Zhongfeng Wang:
Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography. IACR Cryptol. ePrint Arch. 2020: 246 (2020) - [i3]Jing Tian, Piaoyang Wang, Zhe Liu, Jun Lin, Zhongfeng Wang, Johann Großschädl:
Faster Software Implementation of the SIKE Protocol Based on A New Data Representation. IACR Cryptol. ePrint Arch. 2020: 660 (2020) - [i2]Jing Tian, Bo Wu, Zhongfeng Wang:
High-Speed FPGA Implementation of the SIKE Based on An Ultra-Low-Latency Modular Multiplier. IACR Cryptol. ePrint Arch. 2020: 1125 (2020)
2010 – 2019
- 2019
- [j3]Jing Tian
Efficient T-EMS Based Decoding Algorithms for High-Order LDPC Codes. IEEE Access 7: 50980-50992 (2019) - [j2]Wenjie Li
Modified GII-BCH Codes for Low-Complexity and Low-Latency Encoders. IEEE Commun. Lett. 23(5): 785-788 (2019) - [c5]Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang:
Redundancy-Aided Iterative Reliability-Based Majority-Logic Decoding for NB-LDPC Codes. ASICON 2019: 1-4 - [c4]Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang:
A Novel Low-Complexity Joint Coding and Decoding Algorithm for NB-LDPC Codes. ISCAS 2019: 1-5 - [c3]Jing Tian, Jun Lin, Zhongfeng Wang:
Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography. SiPS 2019: 97-102 - [i1]Jing Tian, Zhe Liu, Jun Lin, Zhongfeng Wang, Binjing Li:
High-Speed Modular Multipliers for Isogeny-Based Post-Quantum Cryptography. IACR Cryptol. ePrint Arch. 2019: 1206 (2019) - 2018
- [j1]Jing Tian
A 21.66 Gbps Nonbinary LDPC Decoder for High-Speed Communications. IEEE Trans. Circuits Syst. II Express Briefs 65-II(2): 226-230 (2018) - [c2]Jing Tian, Jun Lin, Zhongfeng Wang:
Analysis of the Dual-Threshold-Based Shrinking Scheme for Efficient NB-LDPC Decoding. APCCAS 2018: 227-230 - [c1]Jing Tian, Jun Lin, Zhongfeng Wang:
An Efficient NB-LDPC Decoding Algorithm for Next-Generation Memories. ISCAS 2018: 1-5
Coauthor Index
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last updated on 2024-11-26 20:49 CET by the dblp team
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