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"Performance and Area Modeling of Complete FPGA Designs in the Presence of ..."

Joonseok Park, Pedro C. Diniz, K. R. Shesha Shayee (2004)

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DOI: 10.1109/TC.2004.101

access: closed

type: Journal Article

metadata version: 2020-06-15

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  - https://dblp.org/rec/journals/tc/ParkDS04
Joonseok Park, Pedro C. Diniz, K. R. Shesha Shayee:
Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations. IEEE Trans. Computers 53(11): 1420-1435 (2004)

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