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Joonseok Park
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2020 – today
- 2023
- [j10]Joonseok Park, Sumin Jeong
, Keunhyuk Yeom:
Smart Contract Broker: Improving Smart Contract Reusability in a Blockchain Environment. Sensors 23(13): 6149 (2023) - [j9]Jemin Kim, Joonseok Park
Enhancing Security of Web-Based IoT Services via XSS Vulnerability Detection. Sensors 23(23): 9407 (2023)
2010 – 2019
- 2019
- [j8]Hyoungseok Kim, Joonseok Park:
Efficient video quality assessment for on-demand video transcoding using intensity variation analysis. J. Supercomput. 75(4): 1751-1765 (2019) - 2015
- [j7]Joonseok Park, Pedro C. Diniz
Program-Invariant Checking for Soft-Error Detection using Reconfigurable Hardware. ACM Trans. Reconfigurable Technol. Syst. 9(1): 1:1-1:13 (2015) - 2014
- [j6]Min-Kook Choi
Event classification for vehicle navigation system by regional optical flow analysis. Mach. Vis. Appl. 25(3): 547-559 (2014) - [c18]Joonseok Park, Pedro C. Diniz:
Evaluating High-Level Program Invariants Using Reconfigurable Hardware. ARC 2014: 121-132 - 2011
- [j5]Joonseok Park, Pedro C. Diniz
Data Reorganization and Prefetching of Pointer-Based Data Structures. IEEE Des. Test Comput. 28(4): 38-47 (2011)
2000 – 2009
- 2009
- [c17]Jaeyoung Yi, Karam Park, Joonseok Park, Won Woo Ro:
Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm. ARC 2009: 181-192 - 2008
- [j4]Won Woo Ro, Jaeyoung Yi, Joon-Sang Park
Simultaneous thin-thread processors for low-power embedded systems. IEICE Electron. Express 5(19): 802-808 (2008) - [j3]Joon-Sang Park
Delay Analysis of Car-to-Car Reliable Data Delivery Strategies Based on Data Mulling with Network Coding. IEICE Trans. Inf. Syst. 91-D(10): 2524-2527 (2008) - 2007
- [c16]Joonseok Park, Pedro C. Diniz:
Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations. ARC 2007: 97-109 - 2005
- [j2]Pedro C. Diniz
Automatic mapping of C to FPGAs with the DEFACTO compilation and synthesis system. Microprocess. Microsystems 29(2-3): 51-62 (2005) - 2004
- [j1]Joonseok Park, Pedro C. Diniz
Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations. IEEE Trans. Computers 53(11): 1420-1435 (2004) - [c15]Nastaran Baradaran, Joonseok Park, Pedro C. Diniz:
Data Reuse in Configurable Architectures with RAM Blocks: Extended Abstract. FPL 2004: 1113-1115 - [c14]Nastaran Baradaran, Joonseok Park, Pedro C. Diniz:
Compiler reuse analysis for the mapping of data in FPGAs with RAM blocks. FPT 2004: 145-152 - [c13]Nastaran Baradaran, Pedro C. Diniz, Joonseok Park:
Extending the Applicability of Scalar Replacement to Multiple Induction Variables. LCPC 2004: 455-469 - 2003
- [c12]Pedro C. Diniz, Joonseok Park:
Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures. FCCM 2003: 207-217 - [c11]K. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz:
Performance and Area Modeling of Complete FPGA Designs in the presence of Loop Transformations. FCCM 2003: 296 - [c10]Joonseok Park, Pedro C. Diniz:
Synthesis and Estimation of Memory Interfaces for FPGA-based Reconfigurable Computing Engines. FCCM 2003: 297-299 - [c9]Pedro C. Diniz, Joonseok Park:
Using FPGAs for data and reorganization engines: preliminary results for spatial pointer-based data structures. FPGA 2003: 242 - [c8]K. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz:
Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop Transformations. FPL 2003: 313-323 - 2002
- [c7]Pedro C. Diniz, Joonseok Park:
Data reorganization engines for the next generation of system-on-a-chip FPGAs. FPGA 2002: 237-244 - 2001
- [c6]Joonseok Park, Pedro C. Diniz:
An External Memory Interface for FPGA-Based Computing Engines. FCCM 2001: 267-268 - [c5]Pablo Moisset, Pedro C. Diniz, Joonseok Park:
Matching and searching analysis for parallel hardware implementation on FPGAs. FPGA 2001: 125-133 - [c4]Joonseok Park, Pedro C. Diniz:
Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines. ISSS 2001: 221-226 - [c3]Pedro C. Diniz, Mary W. Hall
Bridging the Gap between Compilation and Synthesis in the DEFACTO System. LCPC 2001: 52-70 - 2000
- [c2]Pedro C. Diniz, Joonseok Park:
Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines. FCCM 2000: 91-100
1990 – 1999
- 1999
- [c1]Mary W. Hall
Mapping Irregular Applications to DIVA, a PIM-based Data-Intensive Architecture. SC 1999: 57
Coauthor Index
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