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"Verification work reduction methodology in low-power chip implementation."

Masanori Kurimoto et al. (2012)

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DOI: 10.1145/2390191.2390203

access: closed

type: Journal Article

metadata version: 2018-11-06

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  - https://dblp.org/rec/journals/todaes/KurimotoYNHK12
Masanori Kurimoto, Takeshi Yamamoto, Satoshi Nakano, Atsuto Hanami, Hiroyuki Kondo:
Verification work reduction methodology in low-power chip implementation. ACM Trans. Design Autom. Electr. Syst. 18(1): 12:1-12:15 (2012)

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