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"Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA ..."

Francesco Restuccia et al. (2020)

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DOI: 10.4230/DARTS.6.1.4

access: open

type: Journal Article

metadata version: 2024-02-22

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  - https://dblp.org/rec/journals/darts/RestucciaPBMB20
Francesco Restuccia, Marco Pagani, Alessandro Biondi, Mauro Marinoni, Giorgio C. Buttazzo:
Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact). Dagstuhl Artifacts Ser. 6(1): 04:1-04:3 (2020)

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