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"A 17 × 69 bit multiply and add unit with redundant binary feedback ..."

W. S. Briggs, David W. Matula (1993)

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DOI: 10.1109/ARITH.1993.378096

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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W. S. Briggs, David W. Matula:
A 17 × 69 bit multiply and add unit with redundant binary feedback and single cycle latency. IEEE Symposium on Computer Arithmetic 1993: 163-170

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