Abstract: The authors describe a numeric processor with a kernel that is a tree of redundant binary adders and effects either a 17 /spl times/ 69-b ...

exact redundant binary output and single cycle latency. Feedback paths selectively allow a high- order or low-order part of the adder tree output to be.

Algorithms iteratively using this adder tree kernel for IEEE double extended multiplication, division, and square root; conversions between 18-digit BCD ...

W. S. Briggs, David W. Matula: A 17 × 69 bit multiply and add unit with redundant binary feedback and single cycle latency.

A 17 × 69 bit multiply and add unit with redundant binary feedback and single cycle latency. IEEE Symposium on Computer Arithmetic 1993: 163-170. [+] ...

[1] W.S. Briggs, D.W. Matula, A 17; 69 bit multiply and add unit with redundant binary feedback and single cycle latency, Proceedings 11th Symposium on Computer ...

Reduced Latency IEEE Floating-Point Standard Adder Architectures ... A 17 × 69 Bit Multiply and Add Unit with Redundant Binary Feedback and Single Cycle Latency.

The design of a 64-bit integer multiplier/divider unit ... A 17 /spl times/ 69 bit multiply and add unit with redundant binary feedback and single cycle latency ...

A 17 69 bit multiply and add unit with redundant binary feedback and single cycle latency. Proc 11th Symp Comput Arithmetic 1993:163–70. [5] Briggs WS ...

Design of the IBM RISC System/6000 Floating-Point Execution Unit · A 17 × 69 Bit Multiply and Add Unit with Redundant Binary Feedback and Single Cycle Latency.