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Oliver Schrape
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2020 – today
- 2023
- [b1]Oliver Schrape:
Methodology for standard cell-based design and implementation of reliable and robust hardware systems (Methoden für Standardzellbasiertes Design und Implementierung zuverlässiger und robuster Hardware Systeme). University of Potsdam, Germany, 2023 - [c36]Marko S. Andjelkovic, Oliver Schrape, Anselm Breitenreiter
, Milos Krstic:
SET and SEU Hardened Clock Gating Cell. DCIS 2023: 1-6 - 2022
- [j6]Anselm Breitenreiter
Fast Error Propagation Probability Estimates by Answer Set Programming and Approximate Model Counting. IEEE Access 10: 51814-51825 (2022) - [j5]Marko S. Andjelkovic
Analysis of Single Event Transient Effects in Standard Delay Cells Based on Decoupling Capacitors. J. Circuits Syst. Comput. 31(18): 2240007:1-2240007:24 (2022) - [j4]Marko S. Andjelkovic
A design concept for radiation hardened RADFET readout system for space applications. Microprocess. Microsystems 90: 104486 (2022) - [c35]Lukasz Lopacinski, Alireza Hasani, Goran Panic, Nebojsa Maletic, Oliver Schrape, Jesús Gutiérrez, Milos Krstic
Ultra High-Speed BP Decoder for Polar Codes achieving 1.4 Tbps in 28 nm CMOS. EuCNC 2022: 434-439 - [c34]Lukasz Lopacinski, Alireza Hasani, Goran Panic, Nebojsa Maletic, Oliver Schrape, Jesús Gutiérrez, Milos Krstic
Ultra high speed 802.11n LDPC decoder with seven-stage pipeline in 28 nm CMOS. VTC Spring 2022: 1-5 - 2021
- [j3]Oliver Schrape
Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops. IEEE Trans. Circuits Syst. I Regul. Pap. 68(11): 4796-4809 (2021) - [c33]Marko S. Andjelkovic
A Tunable Single Event Transient Filter Based on Digitally Controlled Capacitive Delay Cells. DFT 2021: 1-6 - [c32]Florian Frankreiter, Anselm Breitenreiter
Power- and Area-optimized Neural Network IC-Design for Academic Education. ICECS 2021: 1-6 - [c31]Anselm Breitenreiter
Reliability Analysis in Less than 200 Lines of Code. LASCAS 2021: 1-4 - [c30]Oliver Schrape, Anselm Breitenreiter
Radiation-Hardness-by-Design Latch-based Triple Modular Redundancy Flip-Flops. LASCAS 2021: 1-4 - [c29]Li Lu
Machine Learning Approach for Accelerating Simulation-based Fault Injection. NorCAS 2021: 1-6 - [i1]Marko S. Andjelkovic, Junchao Chen, Aleksandar Simevski, Oliver Schrape, Milos Krstic, Rolf Kraemer:
Monitoring of Particle Flux and LET Variations with Pulse Stretching Inverters. CoRR abs/2104.01202 (2021) - 2020
- [c28]Felipe A. Kuentzer, Moisés Herrera, Oliver Schrape, Peter A. Beerel, Milos Krstic
Radiation Hardened Click Controllers for Soft Error Resilient Asynchronous Architectures. ASYNC 2020: 78-85 - [c27]Steffen Zeidler, Oliver Schrape, Anselm Breitenreiter
A Glitch-free Clock Multiplexer for Non-Continuously Running Clocks. DSD 2020: 11-15 - [c26]Marko S. Andjelkovic
Design of Radiation Hardened RADFET Readout System for Space Applications. DSD 2020: 484-488 - [c25]Oliver Schrape, Marko S. Andjelkovic
Design Concept for Radiation-Hardening of Triple Modular Redundancy TSPC Flip-Flops. DSD 2020: 616-621 - [c24]Marko S. Andjelkovic
Characterization of Single Event Transient Effects in Standard Delay Cells. ICECS 2020: 1-4 - [c23]Aleksandar Simevski, Oliver Schrape, Carlos Benito
PISA: Power-robust Multiprocessor Design for Space Applications. IOLTS 2020: 1-6 - [c22]Christos Georgakidis, Christos P. Sotiriou, Nikolaos Sketopoulos, Milos Krstic
R-Abax: A Radiation Hardening Legalisation Algorithm Satisfying TMR Spacing Constraints. ISVLSI 2020: 316-321
2010 – 2019
- 2019
- [c21]Oliver Schrape, Anselm Breitenreiter
Aspects on Timing Modeling of Radiation-Hardness by Design Standard Cell-Based △TMR Flip-Flops. DSD 2019: 639-642 - [c20]Anselm Breitenreiter
Selective Fault Tolerance by Counting Gates with Controlling Value. IOLTS 2019: 15-20 - 2018
- [c19]Mahdi Tala, Oliver Schrape, Milos Krstic
Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip. DCIS 2018: 1-6 - [c18]Yuanqing Li, Anselm Breitenreiter
Flip-Flop SEUs Mitigation through Partial Hardening of Internal Latch and Adjustment of Clock Duty Cycle. DDECS 2018: 9-14 - [c17]Oliver Schrape, Anselm Breitenreiter
D-SET Mitigation Using Common Clock Tree Insertion Techniques for Triple-Clock TMR Flip-Flop. DSD 2018: 201-205 - [c16]Mahdi Tala
Interfacing 3D-stacked Electronic and Optical NoCs with Mixed CMOS-ECL Bridges: a Realistic Preliminary Assessment. ACM Great Lakes Symposium on VLSI 2018: 81-86 - [c15]Marko S. Andjelkovic
Use of Decoupling Cells for Mitigation of SET Effects in CMOS Combinational Gates. ICECS 2018: 361-364 - [c14]P. Ostrovsky, Oliver Schrape, Klaus Tittelbach-Helmrich, Frank Herzel, Gunter Fischer, D. Hellmann, P. Borner, A. Loose, P. Hartogh, Dietmar Kissinger:
A Radiation Hardened 16 GS/s Arbitrary Waveform Generator IC for a Submillimeter Wave Chirp-Transform Spectrometer. NORCAS 2018: 1-4 - [c13]Oliver Schrape, Alexey Balashov, Aleksandar Simevski, Carlos Benito
Master-Clone Placement with Individual Clock Tree Implementation - a Case on Physical Chip Design. NORCAS 2018: 1-4 - 2017
- [c12]Oliver Schrape, Manuel Herrmann, Frank Winkler, Milos Krstic
Routing approach for digital, differential bipolar designs using virtual fat-wire boundary pins. DDECS 2017: 122-126 - [c11]P. Ostrovsky, Klaus Tittelbach-Helmrich, Frank Herzel, Oliver Schrape, Gunter Fischer, Dietmar Kissinger, P. Borner, A. Loose, D. Hellmann, P. Hartogh:
A single chip 16 GS/s arbitrary waveform generator in 0.13 μm BiCMOS technology. NORCAS 2017: 1-4 - 2016
- [j2]Steffen Zeidler, Xin Fan, Oliver Schrape, Milos Krstic
An Early Stage Design Flow for Switching Noise Attenuation. J. Circuits Syst. Comput. 25(3): 1640022:1-1640022:21 (2016) - [j1]Xin Fan
Frequency-Domain Optimization of Digital Switching Noise Based on Clock Scheduling. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(7): 982-993 (2016) - [c10]Oliver Schrape, Arkadiusz Koczor, Piotr Penkala, Vladimir Petrovic, Milos Krstic
Implementation of DBFN processor for Synthetic Aperture Radar application. DDECS 2016: 175-179 - 2015
- [c9]Steffen Zeidler, Xin Fan, Oliver Schrape, Milos Krstic
A Design Preconditioning Flow for Low-Noise Circuits. DDECS 2015: 191-196 - 2014
- [c8]Oliver Schrape, Markus Appel, Frank Winkler, Milos Krstic
Low-power design methodology for CML and ECL circuits. PATMOS 2014: 1-5 - 2013
- [c7]Xin Fan, Oliver Schrape, Miroslav Marinkovic, Peter Dahnert, Milos Krstic
GALS Design for Spectral Peak Attenuation of Switching Current. ASYNC 2013: 83-90 - [c6]Oliver Schrape, Markus Appel, Frank Winkler, Milos Krstic
A 12 Gb/s standard cell based ECL 4: 1 serializer with asynchronous parallel interface. ICECS 2013: 1-4 - [c5]Goran Panic, Oliver Schrape, Thomas Basmer, Frank Vater, Klaus Tittelbach-Helmrich:
TNODE: A low power sensor node processor for secure wireless networks. ISSoC 2013: 1-4 - 2012
- [c4]Oliver Schrape, Frank Vater:
Embedded low power clock generator for sensor nodes. NORCHIP 2012: 1-4 - 2011
- [c3]Goran Panic, Thomas Basmer, Oliver Schrape, Steffen Peter, Frank Vater, Klaus Tittelbach-Helmrich:
Sensor node processor for security applications. ICECS 2011: 81-84 - 2010
- [c2]Oliver Schrape, Frank Winkler, Steffen Zeidler, Markus Petri, Eckhard Grass, Ulrich Jagdhold:
An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis. PATMOS 2010: 218-227
2000 – 2009
- 2009
- [c1]Frank Winkler, Gerald Kell, Oliver Schrape, Hans Gustat, Ulrich Jagdhold:
HDL-Synthese und Simulation von Hochgeschwindigkeits-Digitalschaltungen mit gemischten CMOS- und ECL-Bibliotheken. MBMV 2009: 137-145
Coauthor Index
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