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FPGA 2019: Seaside, CA, USA
- Kia Bazargan, Stephen Neuendorffer:
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2019, Seaside, CA, USA, February 24-26, 2019. ACM 2019, ISBN 978-1-4503-6137-8
Tutorial 1
- Stephen Ibanez, Gordon J. Brebner
, Nick McKeown, Noa Zilberman
The P4->NetFPGA Workflow for Line-Rate Packet Processing. 1-9 - Sandeep Dutta, Adnan Yunus, Artem Marisov, Matt Menezes, Somayeh Rahimipour:
Visual System Integrator: Invited Tutorial. 10-13 - Chris Lavin
Build Your Own Domain-specific Solutions with RapidWright: Invited Tutorial. 14-22
Session 1: Machine Learning 1
- Yifan Yang, Qijing Huang
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. 23-32 - Caiwen Ding
REQ-YOLO: A Resource-Aware, Efficient Quantization Framework for Object Detection on FPGAs. 33-42 - Martin Hardieck, Martin Kumm, Konrad Möller, Peter Zipf
Reconfigurable Convolutional Kernels for Neural Networks on FPGAs. 43-52
Session 2: Machine Learning 2
- Sahand Salamat, Mohsen Imani, Behnam Khaleghi, Tajana Rosing:
F5-HD: Fast Flexible FPGA-based Framework for Refreshing Hyperdimensional Computing. 53-62 - Shijie Cao, Chen Zhang, Zhuliang Yao, Wencong Xiao, Lanshun Nie, De-chen Zhan, Yunxin Liu, Ming Wu, Lintao Zhang:
Efficient and Effective Sparse LSTM on FPGA with Bank-Balanced Sparsity. 63-72 - Yao Chen
Cloud-DNN: An Open Framework for Mapping DNN Models to Cloud FPGAs. 73-82
Keynote
- Kees A. Vissers:
Versal: The Xilinx Adaptive Compute Acceleration Platform (ACAP). 83
Session 3: Computing Architectures
- Brian Gaide, Dinesh Gaitonde, Chirag Ravishankar, Trevor Bauer:
Xilinx Adaptive Compute Acceleration Platform: VersalTM Architecture. 84-93 - Andrew Boutros, Mohamed Eldafrawy, Sadegh Yazdanshenas, Vaughn Betz:
Math Doesn't Have to be Hard: Logic Block Architectures to Enhance Low-Precision Multiply-Accumulate on FPGAs. 94-103 - Zhe Chen, Hugh T. Blair, Jason Cong:
LANMC: LSTM-Assisted Non-Rigid Motion Correction on FPGA for Calcium Image Stabilization. 104-109 - Daniel Holanda Noronha, Ruizhe Zhao, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton:
On-chip FPGA Debug Instrumentation for Machine Learning Applications. 110-115
Poster Session 1
- Thaddeus Koehn, Peter Athanas:
Scheduling Data in Neural Network Applications. 116 - Tom J. Mannos, Brian Dziki, Moslema Sharif:
Fault Testing a Synthesizable Embedded Processor at Gate Level using UltraScale FPGA Emulation. 116 - Zheming Jin, Hal Finkel:
Base64 Encoding on OpenCL FPGA Platform. 116 - Sasindu Wijeratne, Ashen Ekanayake, Sandaruwan Jayaweera, Danuka Ravishan, Ajith Pasqual:
Scalable High Performance SDN Switch Architecture on FPGA for Core Networks. 117 - Hongzheng Chen, Minghua Shen:
A Deep-Reinforcement-Learning-Based Scheduler for High-Level Synthesis. 117 - Junzhong Shen, Deguang Wang, You Huang, Mei Wen, Chunyuan Zhang:
Accelerating 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System. 117 - Xin He, Liu Ke, Xuan Zhang:
SparseBNN: Joint Algorithm/Hardware Optimization to Exploit Structured Sparsity in Binary Neural Network. 117-118 - Lu Jing, Jun Liu, FuHai Yu:
A Deep Learning Inference Accelerator Based on Model Compression on FPGA. 118 - Feng Shi, Haochen Li, Yuhe Gao, Benjamin Kuschner, Song-Chun Zhu:
Sparse Winograd Convolutional Neural Networks on Small-scale Systolic Arrays. 118 - Ramtin Zand, Ronald F. DeMara:
HSC-FPGA. 118-119 - Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil C. Knag, Raghavan Kumar, Ram Krishnamurthy, Debbie Marr, Sergey Gribok, Bogdan Pasca
Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI. 119 - Minghua Shen, Nong Xiao:
Parrot: A More Effective Parallel Routing Approach to FPGAs. 119 - Weijie You, Chang Wu:
A Reconfigurable Accelerator for Sparse Convolutional Neural Networks. 119 - Xuechao Wei, Yun Liang, Peng Zhang, Cody Hao Yu, Jason Cong:
Overcoming Data Transfer Bottlenecks in DNN Accelerators via Layer-Conscious Memory Managment. 120 - Tianqi Gao, Rob A. Rutenbar:
A Pixel-Parallel Virtual-Image Architecture for High Performance and Power Efficient Graph Cuts Inference. 120 - Jialiang Zhang, Jing Li
Unleashing the Power of Soft Logic for Convolutional Neural Network Acceleration via Product Quantization. 120 - Yanjie Gu, Jian Yu, Tieli Sun, Chen Pan, Zhenhao Feng, Liewei Xu, Chang Wu:
Highly Efficient Sparse Neural Network Computing: Hardware and Software Solutions. 121 - Jyotikrishna Dass
FPGA-based Distributed Edge Training of SVM. 121 - Zhengjie Li, Yuanlong Xiao, Yufan Zhang, Yunbing Pang, Jian Wang, Jinmei Lai:
Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits. 121
Session 4: CAD
- Nima Karimpour Darav, Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu:
Multi-Commodity Flow-Based Spreading in a Commercial Analytic Placer. 122-131 - Wuxi Li, Mehrdad E. Dehkordi, Stephen Yang, David Z. Pan:
Simultaneous Placement and Clock Tree Construction for Modern FPGAs. 132-141 - Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, George A. Constantinides:
EASY: Efficient Arbiter SYnthesis from Multi-threaded Code. 142-151
Session 5: Synthesis
- Maciej Besta, Marc Fischer, Tal Ben-Nun, Johannes de Fine Licht
Substream-Centric Maximum Matchings on FPGA. 152-161 - Lana Josipovic
Speculative Dataflow Circuits. 162-171 - Hui Yan, Zhaoshi Li, Leibo Liu
Constructing Concurrent Data Structures on FPGA with Channels. 172-177 - Yuze Chi, Young-kyu Choi
Rapid Cycle-Accurate Simulator for High-Level Synthesis. 178-183
Poster Session 2
- Lansong Diao, Zhao Jiang, Hao Liang, Chang'an Ye, Kai Chen, Li Ding, Shunli Dou, Meng Sun, Lixue Xia, Jiansong Zhang, Wei Lin:
PAI-FCNN: FPGA Based CNN Inference System. 184 - Katie Lim, Jonathan Balkind, David Wentzlaff:
JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores. 184 - Yun Zhou
MODA-PSO: Towards Fast Hard Block Legalization for Analytical FPGA Placement. 184 - Chen Chen
A PYNQ-compliant Online Platform for Zynq-based DNN Developers. 185 - Fan Yang, Zhan Wang, Xiaoxiao Ma
SwitchAgg: A Further Step Towards In-Network Computation. 185 - Shulin Zeng, Yujun Lin
A Fine-Grained Sparse Accelerator for Multi-Precision DNN. 185 - Carl-Johannes Johnsen, Kenneth Skovhede:
Building FPGA State Machines from Sequential Code. 186 - Dario Korolija, Mirjana Stojilovic:
Design and Implementation of a Deterministic FPGA Router on a CPU+FPGA Acceleration Platform. 186 - Hiroki Nakahara, Akira Jinguji, Masayuki Shimoda, Shimpei Sato:
An FPGA-based Fine Tuning Accelerator for a Sparse CNN. 186 - Jiafeng Xie, Chiou-Yng Lee:
Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity. 187 - Jie Liu
Dataflow Systolic Array Implementations of Matrix Decomposition Using High Level Synthesis. 187 - Liqiang Lu, Yun Liang, Ruirui Huang, Wei Lin, Xiaoyuan Cui, Jiansong Zhang:
Speedy: An Accelerator for Sparse Convolutional Neural Networks on FPGAs. 187 - Yu Xing
DNNVM: End-to-End Compiler Leveraging Operation Fusion on FPGA-based CNN Accelerators. 187-188 - Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang:
A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms. 188 - Anastasiia Kucherenko, Stefan Nikolic
On Feasibility of FPGAs Without Dedicated Programmable Interconnect Structure. 188 - Yazhu Lan, Qingli Guo, Guohe Zhang, Yuanchao Xu, Kent W. Nixon, Hai Helen Li, Yiran Chen:
Fast Confidence Detection: One Hot Way to Detect Adversarial Attacks via Sensor Pattern Noise Fingerprinting. 188-189 - Zhucheng Tang, Guojie Luo, Ming Jiang:
FTConv: FPGA Acceleration for Transposed Convolution Layers in Deep Neural Networks. 189 - Kaiyuan Guo, Shuang Liang, Jincheng Yu, Xuefei Ning, Wenshuo Li, Yu Wang, Huazhong Yang:
Compressed CNN Training with FPGA-based Accelerator. 189 - Juan Escobedo, Mingjie Lin:
Optimizing Order-Associative Kernel Computation with Joint Memory Banking and Data Reuse. 189-190 - Konstantinos Maragos, George Lentaris, Dimitrios Soudris, Vasilis F. Pavlidis:
PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAs. 190 - Zachary Sherer, Eric Finnerty, Yan Luo, Hang Liu:
Software Hardware Co-Optimized BFS on FPGAs. 190
Tutorial 2
- Ephrem Wu
Compute-Efficient Neural-Network Acceleration. 191-200
Panel
- Deming Chen:
FPGAs in Supercomputers: Opportunity or Folly? 201
Tutorial 3
- Martin Langhammer, Gregg Baeckler, Sergey Gribok:
Fractal Synthesis: Invited Tutorial. 202-211
Session 6: Networks and NOCs
- Ian Swarbrick, Dinesh Gaitonde, Sagheer Ahmad, Brian Gaide, Ygal Arbel:
Network-on-Chip Programmable Platform in VersalTM ACAP Architecture. 212-221 - Tushar Garg, Saud Wasly
HopliteBuf: FPGA NoCs with Provably Stall-Free FIFOs. 222-231 - Daniel Rozhko, Paul Chow:
The Network Management Unit (NMU): Securing Network Access for Direct-Connected FPGAs. 232-241
Session 7: Heterogenous Platforms
- Yi-Hsiang Lai, Yuze Chi, Yuwei Hu, Jie Wang, Cody Hao Yu, Yuan Zhou, Jason Cong, Zhiru Zhang
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. 242-251 - Sajjad Taheri, Payman Behnam, Eli Bozorgzadeh, Alexander V. Veidenbaum, Alexandru Nicolau:
AFFIX: Automatic Acceleration Framework for FPGA Implementation of OpenVX Vision Algorithms. 252-261 - Nariman Eskandari, Naif Tarafdar, Daniel Ly-Ma, Paul Chow:
A Modular Heterogeneous Stack for Deploying FPGAs and CPUs in the Data Center. 262-271
Session 8: Devices and Security
- Andrew M. Keller, Michael J. Wirthlin:
Impact of Soft Errors on Large-Scale FPGA Cloud Computing. 272-281 - Aimee Coughlin
Breaking the Trust Dependence on Third Party Processes for Reconfigurable Secure Hardware. 282-291 - George Provelengios, Chethan Ramesh, Shivukumar B. Patil, Ken Eguro, Russell Tessier, Daniel E. Holcomb:
Characterization of Long Wire Data Leakage in Deep Submicron FPGAs. 292-297 - Shanquan Tian, Jakub Szefer:
Temporal Thermal Covert Channels in Cloud FPGAs. 298-303
Poster Session 3
- Anping He, Jinlin Zhang, Lvying Yu, Pengfei Li, Lian Li:
How to Accelerate FPGA Application in an Asynchronous Way? 304 - Zheming Jin, Hal Finkel:
Nuclear Reactor Simulations on OpenCL FPGA Platform. 304 - Dan Cristian Turicu, Octavian Cret, Lucia Vacariu:
Storage Mirroring for Bare-Metal Systems on FPGA Devices. 304-305 - Javier M. Duarte, Song Han, Philip C. Harris, Sergo Jindariani, Edward Kreinar, Benjamin Kreis, Vladimir Loncar, Jennifer Ngadiuba, Maurizio Pierini, Dylan S. Rankin, Ryan A. Rivera, Sioni Summers, Nhan Tran, Zhenbin Wu:
Fast Inference of Deep Neural Networks for Real-time Particle Physics Applications. 305 - Weiwen Jiang, Xinyi Zhang, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Lei Yang, Yiyu Shi, Jingtong Hu:
XFER: A Novel Design to Achieve Super-Linear Performance on Multiple FPGAs for Real-Time AI. 305 - Elham Azari, Aykut Dengi, Sarma B. K. Vrudhula:
An Energy-Efficient FPGA Implementation of an LSTM Network Using Approximate Computing. 305-306 - Cheng Fu, Shilin Zhu, Hao Su, Ching-En Lee, Jishen Zhao:
Towards Fast and Energy-Efficient Binarized Neural Network Inference on FPGA. 306 - Sahan Bandara, Alan Ehret, Donato Kava, Michel A. Kinsy:
BRISC-V: An Open-Source Architecture Design Space Exploration Toolbox. 306 - Dallon Glick, Jesse Grigg, Brent E. Nelson, Michael J. Wirthlin:
Maverick: A Stand-alone CAD Flow for Xilinx 7-Series FPGAs. 306-307 - Venkat Konda:
Hierarchical FPGA Fabrics using 2D-Benes-BFT-Pyramid Network Layouts with Optimizations. 307 - Venkat Konda:
Flat FPGA Fabrics Derived from 2D-Benes-BFT-Pyramid Networks with Optimizations and Enhancements. 307 - Michael P. Kapralos
HOTMeTaL: Hardware Optimization Tool for Memory Table and Logic Conversion. 307-308 - Ke Zhang, Yisong Chang, Mingyu Chen, Yungang Bao, Zhiwei Xu:
Engaging Heterogeneous FPGAs in the Cloud. 308 - Gurshaant Singh Malik, Nachiket Kapre:
Enhancing Butterfly Fat Tree NoCs for FPGAs with Lightweight Flow Control. 308 - Sahithi Rampalli, Natasha Sehgal, Ishita Bindlish, Tanya Tyagi, Pawan Kumar:
Efficient FPGA Implementation of Conjugate Gradient Methods for Laplacian System using HLS. 308-309 - Chia-Wei Chang, Zi-Qi Zhong, Jing-Jia Liou:
A FPGA Implementation of Farneback Optical Flow by High-Level Synthesis. 309 - Sebastian Vogel, Jannik Springer, Andre Guntoro, Gerd Ascheid:
Efficient Acceleration of CNNs for Semantic Segmentation on FPGAs. 309
Session 9: Memory
- Mikhail Asiatici, Paolo Ienne:
Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs. 310-319 - Zhiyuan Shao, Ruoshi Li, Diqing Hu, Xiaofei Liao, Hai Jin:
Improving Performance of Graph Processing on FPGA-DRAM Platform by Two-level Vertex Caching. 320-329 - David Biancolin, Sagar Karandikar, Donggyu Kim, Jack Koenig, Andrew Waterman, Jonathan Bachrach, Krste Asanovic:
FASED: FPGA-Accelerated Simulation and Evaluation of DRAM. 330-339
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