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Cosimo Antonio Prete
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- affiliation: University of Pisa, Italy
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2020 – today
- 2024
- [j46]Antonio Di Tecco
, Pierfrancesco Foglia
Video Quality Prediction: An Exploratory Study With Valence and Arousal Signals. IEEE Access 12: 36558-36576 (2024) - 2023
- [c39]Diana Orlandi
U-Nets and Multispectral Images for Detecting the Surface Water of Rivers via SAR Images. GISTAM (Selected Papers) 2023: 1-13 - 2022
- [c38]Mario G. C. A. Cimino
Using Emotion Recognition and Temporary Mobile Social Network in On-Board Services for Car Passengers. SMARTGREENS/VEHITS (Selected Papers) 2022: 158-171 - [c37]Mario G. C. A. Cimino, Antonio Di Tecco
in-Car Entertainment via Group-wise Temporary Mobile Social Networking. VEHITS 2022: 432-437 - 2021
- [j45]Gabriele Antonio De Vitis, Pierfrancesco Foglia
A pre-processing technique to decrease inspection time in glass tube production lines. IET Image Process. 15(10): 2179-2191 (2021) - [j44]Gabriele Antonio De Vitis, Antonio Di Tecco
Fast Blob and Air Line Defects Detection for High Speed Glass Tube Production Lines. J. Imaging 7(11): 223 (2021) - 2020
- [j43]Gabriele Antonio De Vitis, Pierfrancesco Foglia
Row-level algorithm to improve real-time performance of glass tube defect detection in the production phase. IET Image Process. 14(12): 2911-2921 (2020)
2010 – 2019
- 2019
- [c36]Gabriele Antonio De Vitis, Pierfrancesco Foglia
Algorithms for the Detection of Blob Defects in High Speed Glass Tube Production Lines. IWASI 2019: 97-102 - 2018
- [j42]Sandro Bartolini, Pierfrancesco Foglia
Exploring the relationship between architectures and management policies in the design of NUCA-based chip multicore systems. Future Gener. Comput. Syst. 78: 481-501 (2018) - [c35]Mario G. C. A. Cimino, Federico Dalla Bona, Pierfrancesco Foglia
Stock Price Forecasting Over Adaptive Timescale Using Supervised Learning and Receptive Fields. MIKE 2018: 279-288 - 2015
- [j41]Stefano Campanelli, Pierfrancesco Foglia
An architecture to integrate IEC 61131-3 systems in an IEC 61499 distributed solution. Comput. Ind. 72: 47-67 (2015) - 2014
- [j40]Gianluca Dini
Social and Q&A interfaces for app download. Inf. Process. Manag. 50(4): 584-598 (2014) - [j39]Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia
Evaluation of Leakage Reduction Alternatives for Deep Submicron Dynamic Nonuniform Cache Architecture Caches. IEEE Trans. Very Large Scale Integr. Syst. 22(1): 185-190 (2014) - 2013
- [j38]Gianluca Dini
A Social-Feedback Enriched Interface for Software Download. J. Organ. End User Comput. 25(1): 24-42 (2013) - 2012
- [j37]Massimiliano Annoni
A real-time configurable NURBS interpolator with bounded acceleration, jerk and chord error. Comput. Aided Des. 44(6): 509-521 (2012) - [c34]Stefano Campanelli, Pierfrancesco Foglia
Integration of existing IEC 61131-3 systems in an IEC 61499 distributed solution. ETFA 2012: 1-8 - 2011
- [j36]Sandro Bartolini, Pierfrancesco Foglia
Eighth MEDEA Workshop. Trans. High Perform. Embed. Archit. Compil. 3: 91-92 (2011) - [r2]Alessandro Bardine, Pierfrancesco Foglia, Cosimo Antonio Prete, Marco Solinas:
NUMA Caches. Encyclopedia of Parallel Computing 2011: 1329-1338 - 2010
- [j35]Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia
Way adaptable D-NUCA caches. Int. J. High Perform. Syst. Archit. 2(3/4): 215-228 (2010) - [c33]Pierfrancesco Foglia
Re-NUCA: Boosting CMP Performance Through Block Replication. DSD 2010: 199-206 - [c32]Alessandro Bardine, Stefano Campanelli, Pierfrancesco Foglia
NURBS interpolator with confined chord error and tangential and centripetal acceleration control. ICUMT 2010: 489-496 - [c31]Sandro Bartolini, Pierfrancesco Foglia
Feedback-Driven Restructuring of Multi-threaded Applications for NUCA Cache Performance in CMPs. SBAC-PAD 2010: 87-94
2000 – 2009
- 2009
- [j34]Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia
Impact of on-chip network parameters on nuca cache performances. IET Comput. Digit. Tech. 3(5): 501-512 (2009) - [c30]Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete:
A power-efficient migration mechanism for D-NUCA caches. DATE 2009: 598-601 - [c29]Pierfrancesco Foglia
An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload. DSD 2009: 26-33 - [c28]Pierfrancesco Foglia
Analysis of Performance Dependencies in NUCA-Based CMP Systems. SBAC-PAD 2009: 49-56 - [e4]Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete:
Proceedings of the 10th workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '09, Raleigh, North Carolina, USA, September 13, 2009. ACM 2009, ISBN 978-1-60558-830-8 [contents] - 2008
- [c27]Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia
Leveraging Data Promotion for Low Power D-NUCA Caches. DSD 2008: 307-316 - [c26]Alessio Bechini
Special track on Embedded Systems: Applications, Solutions, and Techniques: editorial message. SAC 2008: 1476 - [c25]Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia
Performance Sensitivity of NUCA Caches to On-Chip Network Parameters. SBAC-PAD 2008: 167-174 - [e3]Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, Roberto Giorgi:
Proceedings of the 9th workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '08, Toronto, Canada, October 26, 2008. ACM 2008, ISBN 978-1-60558-243-6 [contents] - 2007
- [j33]Pierfrancesco Foglia
Assisting e-government users with animated talking faces. Interactions 14(1): 24-26 (2007) - [j32]Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete:
MEmory performance: DEaling with applications, systems and architecture. SIGARCH Comput. Archit. News 35(4): 4-5 (2007) - [j31]Alessandro Bardine, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete, Per Stenström:
Improving power efficiency of D-NUCA caches. SIGARCH Comput. Archit. News 35(4): 53-58 (2007) - [c24]Alessandro Bardine, Pierfrancesco Foglia
Analysis of static and dynamic energy consumption in NUCA caches: initial results. MEDEA@PACT 2007: 105-112 - [e2]Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, Roberto Giorgi:
Proceedings of the 2007 workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '07, Brasov, Romania, September 16, 2007. ACM 2007, ISBN 978-1-59593-807-7 [contents] - [r1]Pierfrancesco Foglia, Cosimo Antonio Prete, Michele Zanda:
Modelling Public Administration Portals. Encyclopedia of Portal Technologies and Applications 2007: 606-614 - 2006
- [j30]Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete:
Embedded processors and systems: Architectural issues and solutions for emerging applications. J. Embed. Comput. 2(1): 1-3 (2006) - [j29]Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete:
Memory performance: dealing with applications, systems and architecture. SIGARCH Comput. Archit. News 34(1): 1-2 (2006) - [j28]Alessandro Bardine, Alessio Bechini
Analysis of embedded video coder systems: a system-level approach. SIGARCH Comput. Archit. News 34(1): 71-76 (2006) - [c23]Alessio Bechini
Editorial message for the special track on embedded systems: applications, solutions, and techniques. SAC 2006: 889-890 - 2005
- [j27]Pierfrancesco Foglia, Daniele Mangano, Cosimo Antonio Prete:
A cache design for high performance embedded systems. J. Embed. Comput. 1(4): 587-597 (2005) - [j26]Pierfrancesco Foglia
Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload. J. Parallel Distributed Comput. 65(3): 289-306 (2005) - [j25]Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete:
Guests editor's introduction. SIGARCH Comput. Archit. News 33(3): 1-2 (2005) - [j24]Sandro Bartolini, Cosimo Antonio Prete:
Optimizing instruction cache performance of embedded systems. ACM Trans. Embed. Comput. Syst. 4(4): 934-965 (2005) - [c22]Pierfrancesco Foglia
A NUCA Model for Embedded Systems Cache Design. ESTIMedia 2005: 41-46 - [c21]Alessio Bechini
Editorial message for the special track on embedded systems: applications, solutions, and techniques. SAC 2005: 836-837 - [c20]Cosimo Antonio Prete, Pierfrancesco Foglia, Michele Zanda:
An Innovative Tool to Easily Get Usable Web Sites. WEBIST 2005: 373-376 - 2004
- [j23]Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete:
Speeding-up multiprocessors running DBMS workloads through coherence protocols. Int. J. High Perform. Comput. Netw. 1(1/2/3): 17-32 (2004) - [j22]Alessio Bechini
Guest Editors' Introduction: Opportunities and Challenges in Embedded Systems. IEEE Micro 24(4): 8-9 (2004) - [j21]Sandro Bartolini, Cosimo Antonio Prete:
A proposal for input-sensitivity analysis of profile-driven optimizations on embedded applications. SIGARCH Comput. Archit. News 32(3): 70-77 (2004) - [c19]Alessio Bechini
Editorial message for the special track on embedded systems: applications, solutions, and techniques. SAC 2004: 819-820 - [e1]Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete:
Proceedings of the 2004 workshop on MEmory performance - DEaling with Applications , systems and architecture, MEDEA '04, Antibes Juan-les-Pins, France, September 29 - October 3, 2004. ACM 2004 [contents] - 2003
- [j20]Alessio Bechini
Fine-grain design space exploration for a cartographic SoC multiprocessor. SIGARCH Comput. Archit. News 31(1): 85-92 (2003) - [c18]Alessio Bechini
Embedded Systems Track Editorial. SAC 2003: 659-660 - 2002
- [j19]Sandro Bartolini, Cosimo Antonio Prete:
A cache-aware program transformation technique suitable for embedded systems. Inf. Softw. Technol. 44(13): 783-795 (2002) - [j18]Alessio Bechini
Performance-steered design of software architectures for embedded multicore systems. Softw. Pract. Exp. 32(12): 1155-1173 (2002) - [c17]Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete:
Boosting the Performance of Three-Tier Web Servers Deploying SMP Architecture. NETWORKING Workshops 2002: 134-146 - [c16]Irina Branovic, Roberto Giorgi, Cosimo Antonio Prete:
Web-based training on computer architecture: the case for JCachesim. WCAE 2002: 10 - [c15]Alessio Bechini
Use of a CORBA/RMI gateway: characterization of communication overhead. Workshop on Software and Performance 2002: 150-156 - 2001
- [j17]Alessio Bechini
Behavior investigation of concurrent Java programs: an approach based on source-code instrumentation. Future Gener. Comput. Syst. 18(2): 307-316 (2001) - [j16]Sandro Bartolini, Roberto Giorgi, Jelica Protic, Cosimo Antonio Prete, Mateo Valero:
Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction. SIGARCH Comput. Archit. News 29(5): 9-12 (2001) - [c14]Pierfrancesco Foglia
Evaluating Optimizing for Multiprocessors E-Commerce Server Running TPC-W Workload. HICSS 2001 - [c13]Sandro Bartolini, Cosimo Antonio Prete:
An Object Level Transformation Technique to Improve the Performance of Embedded Applications. SCAM 2001: 26-34 - 2000
- [c12]Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete:
Performance Analysis of Electronic Commerce Multiprocessor Server. HICSS 2000
1990 – 1999
- 1999
- [j15]Roberto Giorgi, Cosimo Antonio Prete:
PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors. IEEE Trans. Parallel Distributed Syst. 10(7): 742-763 (1999) - [c11]Alessio Bechini
Dealing with Non-Determinism in Communications within Java Applications. EUROMICRO 1999: 2350- - [c10]Pierfrancesco Foglia
Process Migration Effects on Memory Performance of Multiprocessor. HiPC 1999: 133-142 - 1998
- [c9]Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete:
Analysis of Sharing Overhead in Shared Memory Multiprocessors. HICSS (7) 1998: 776-777 - [c8]Roberto Giorgi, Cosimo Antonio Prete:
An educational environment for designing and performance tuning of embedded systems. WCAE@ISCA 1998: 29 - 1997
- [j14]Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi:
Trace Factory: generating workloads for trace-driven simulation of shared-bus multiprocessors. IEEE Concurrency 5(4): 54-68 (1997) - [j13]Cosimo Antonio Prete, Marco Graziano, Francesco Lazzarini:
The ChARM tool for tuning embedded systems. IEEE Micro 17(4): 67-76 (1997) - [c7]Roberto Giorgi
A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessors. HICSS (1) 1997: 266-275 - [c6]Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Prina:
Cache memory design for embedded systems based on program locality analysis. MSE 1997: 16-18 - 1996
- [c5]Roberto Giorgi, Cosimo Antonio Prete, Luigi M. Ricciardi, Gianpaolo Prina:
A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors. EUROMICRO 1996: 207-214 - 1995
- [j12]Alberto Bartoli
Reusing sequential software in a distributed environment. Distributed Syst. Eng. 2(1): 2-13 (1995) - [j11]Alberto Bartoli
Graphical design of distributed applications through reusable components. IEEE Parallel Distributed Technol. Syst. Appl. 3(1): 37-50 (1995) - [j10]Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi:
A Selective Invalidation Strategy for Cache Coherence. IEICE Trans. Inf. Syst. 78-D(10): 1316-1320 (1995) - [j9]Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi:
A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems. IEEE Trans. Parallel Distributed Syst. 6(9): 915-929 (1995) - [c4]Cosimo Antonio Prete, Luigi M. Ricciardi, Gianpaolo Prina:
Reducing coherence-related overhead in multiprocessor systems. PDP 1995: 444-451 - [c3]Cosimo Antonio Prete, Gianpaolo Prina:
Experiences in using a cache simulation tool in an advanced computer architecture course. WCAE@ISCA 1995: 10 - 1994
- [c2]Cosimo Antonio Prete:
Cachesim: A Graphical Software Environment to Support the Teaching of Computer Systems with Cache Memories. CSEE 1994: 317-327 - 1992
- [c1]Cosimo Antonio Prete:
A process cache memory for tightly coupled multiprocessor systems. ACM Southeast Regional Conference 1992: 131-138 - 1991
- [j8]Cosimo Antonio Prete:
RST cache memory design for a highly coupled multiprocessor system. IEEE Micro 11(2): 16-19 (1991) - 1990
- [j7]Cosimo Antonio Prete:
A new solution of coherence protocol for tightly coupled multiprocessor systems. Microprocessing and Microprogramming 30(1-5): 207-214 (1990) - [j6]Paolo Ancilotti, Beatrice Lazzerini
A Distributed Commit Protocol for a Multicomputer System. IEEE Trans. Computers 39(5): 718-724 (1990)
1980 – 1989
- 1989
- [j5]Andrea Domenici
A protocol for resource locking and deadlock detection in a multi-user environment. Microprocessing and Microprogramming 27(1-5): 431-437 (1989) - 1988
- [j4]Beatrice Lazzerini
Event-driven debugging for distributed software. Microprocess. Microsystems 12(1): 33-39 (1988) - 1986
- [j3]Paolo Corsini, Cosimo Antonio Prete:
Software development tool for target systems and EPROM programmers within a Unix environment. Microprocess. Microsystems 10(10): 540-542 (1986) - [j2]Paolo Corsini, Cosimo Antonio Prete:
Multibug: Interative Debugging in Distributed Systems. IEEE Micro 6(3): 26-33 (1986) - 1985
- [j1]Paolo Corsini, Cosimo Antonio Prete, Luca Simoncini:
MuTEAM: An experience in the design of robust multiprocessor systems. Comput. Syst. Sci. Eng. 1(1): 23-35 (1985)
Coauthor Index
[j46] [c39] [c38] [c37] [j45] [j44] [j43] [c36] [j42] [c35] [j41] [j40] [j39] [j38] [j37] [c34] [j36] [r2] [j35] [c33] [c32] [c31] [j34] [c30] [c29] [c28] [e4] [c27] [c25] [e3] [j33] [j32] [j31] [c24] [e2] [r1] [j30] [j29] [j28] [j27] [j26] [j25] [c22] [c20] [j23] [e1] [j20] [c17] [c15] [c14] [c12] [c10] [c9]
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last updated on 2024-10-07 21:21 CEST by the dblp team
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