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Sandro Bartolini
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2020 – today
- 2024
- [c20]Mirco Mannino
, Yinting Huang
Integration of RISC-V Page Table Walk in gem5 SE Mode. RAPIDO@HiPEAC 2024: 22-28 - 2023
- [j27]Biagio Peccerillo
IXIAM: ISA EXtension for Integrated Accelerator Management. IEEE Access 11: 33768-33791 (2023) - [j26]Mirco Mannino
Analysis and Optimization of Direct Convolution Execution on Multi-Core Processors. IEEE Access 11: 57514-57528 (2023) - [j25]Davide Privitera
Adaptive Dosing Control System Through ARIMA Model for Peristaltic Pumps. IEEE Access 11: 99558-99572 (2023) - [c19]Mirco Mannino
Energy and Performance Improvements for Convolutional Accelerators Using Lightweight Address Translation Support. CF 2023: 84-90 - [c18]Alessio Medaglini
Software-Based Fault-Detection Technique for Object Tracking in Autonomous Vehicles. MECO 2023: 1-7 - 2022
- [j24]Elham Cheshmikhani
A General Framework for Accelerator Management Based on ISA Extension. IEEE Access 10: 120702-120713 (2022) - [j23]Biagio Peccerillo
Flexible task-DAG management in PHAST library: Data-parallel tasks and orchestration support for heterogeneous systems. Concurr. Comput. Pract. Exp. 34(2) (2022) - [j22]Pablo Antonio Martínez
Applying Intel's oneAPI to a machine learning case study. Concurr. Comput. Pract. Exp. 34(13) (2022) - [j21]Pablo Antonio Martínez
Performance portability in a real world application: PHAST applied to Caffe. Int. J. High Perform. Comput. Appl. 36(3): 419-439 (2022) - [j20]Biagio Peccerillo
A survey on hardware accelerators: Taxonomy, trends, challenges, and perspectives. J. Syst. Archit. 129: 102561 (2022) - 2020
- [i1]Eduardo José Gómez-Hernández
Using PHAST to port Caffe library: First experiences and lessons learned. CoRR abs/2005.13076 (2020)
2010 – 2019
- 2019
- [j19]Biagio Peccerillo
Parallel bitsliced AES through PHAST: a single-source high-performance library for multi-cores and GPUs. J. Cryptogr. Eng. 9(2): 159-171 (2019) - [j18]Biagio Peccerillo
PHAST - A Portable High-Level Modern C++ Programming Library for GPUs and Multi-Cores. IEEE Trans. Parallel Distributed Syst. 30(1): 174-189 (2019) - [c17]Biagio Peccerillo
Task-DAG Support in Single-Source PHAST Library: Enabling Flexible Assignment of Tasks to CPUs and GPUs in Heterogeneous Architectures. PMAM@PPoPP 2019: 91-100 - 2018
- [j17]Sandro Bartolini, Pierfrancesco Foglia
Exploring the relationship between architectures and management policies in the design of NUCA-based chip multicore systems. Future Gener. Comput. Syst. 78: 481-501 (2018) - [j16]Sandro Bartolini, Alessandro Mecocci, Alessandro Pozzebon
Augmented Virtuality for Coastal Management: A Holistic Use of In Situ and Remote Sensing for Large Scale Definition of Coastal Dynamics. ISPRS Int. J. Geo Inf. 7(3): 92 (2018) - [j15]Paolo Grani
Scalable Path-Setup Scheme for All-Optical Dynamic Circuit Switched NoCs in Cache Coherent CMPs. ACM J. Emerg. Technol. Comput. Syst. 14(1): 12:1-12:27 (2018) - [p2]Sandro Bartolini, Biagio Peccerillo
Parallel Programming in Cyber-Physical Systems. Cyber-Physical Systems Security 2018: 111-134 - 2017
- [c16]Biagio Peccerillo
PHAST Library - Enabling Single-Source and High Performance Code for GPUs and Multi-cores. HPCS 2017: 715-718 - 2016
- [e5]Sören Sonntag, Sandro Bartolini, Giorgos Dimitrakopoulos, José M. García:
Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC 2016, Prague, Czech Republic, January 18, 2016. ACM 2016, ISBN 978-1-4503-4084-7 [contents] - 2015
- [c15]Paolo Grani
Boosting multi-socket cache-coherency with low-latency silicon photonic interconnects. ICNC 2015: 830-836 - 2014
- [j14]Sandro Bartolini, José M. García
Exploiting silicon photonics for energy-efficient heterogeneous parallel architectures. Concurr. Comput. Pract. Exp. 26(15): 2489-2491 (2014) - [j13]Antonio García-Guirado, Ricardo Fernández Pascual
Managing resources dynamically in hybrid photonic-electronic networks-on-chip. Concurr. Comput. Pract. Exp. 26(15): 2530-2550 (2014) - [j12]Paolo Grani
Design Options for Optical Ring Interconnect in Future Client Devices. ACM J. Emerg. Technol. Comput. Syst. 10(4): 30:1-30:25 (2014) - [c14]Luca Ramini, Alberto Ghiribaldi, Paolo Grani, Sandro Bartolini, Hervé Tatenguem Fankem
Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline. DATE 2014: 1-6 - [c13]Paolo Grani
Simultaneous Optical Path-Setup for Reconfigurable Photonic Networks in Tiled CMPs. HPCC/CSS/ICESS 2014: 482-485 - [c12]Sandro Bartolini, Iacopo Casini, Paolo Detti
Solving Graph Partitioning Problems Arising in Tagless Cache Management. ISCO 2014: 50-61 - [c11]Luca Ramini, Hervé Tatenguem Fankem
Towards compelling cases for the viability of silicon-nanophotonic technology in future manycore systems. NOCS 2014: 170-171 - 2013
- [c10]Luca Ramini, Paolo Grani, Sandro Bartolini, Davide Bertozzi:
Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis. DATE 2013: 1589-1594 - [c9]Sandro Bartolini, Luca Lusnig, Enrico Martinelli:
Olympic: A Hierarchical All-Optical Photonic Network for Low-Power Chip Multiprocessors. DSD 2013: 56-59 - [c8]Sandro Bartolini, Paolo Grani
Co-tuning of a hybrid electronic-optical network for reducing energy consumption in embedded CMPs. MES 2013: 9-16 - 2012
- [c7]Sandro Bartolini, Paolo Grani
A Simple On-Chip Optical Interconnection for Improving Performance of Coherency Traffic in CMPs. DSD 2012: 312-318 - 2011
- [j11]Sandro Bartolini, Pierfrancesco Foglia
Eighth MEDEA Workshop. Trans. High Perform. Embed. Archit. Compil. 3: 91-92 (2011) - [c6]Timothy M. Jones
Link-time optimization for power efficiency in a tagless instruction cache. CGO 2011: 32-41 - 2010
- [c5]Sandro Bartolini, Pierfrancesco Foglia
Feedback-Driven Restructuring of Multi-threaded Applications for NUCA Cache Performance in CMPs. SBAC-PAD 2010: 87-94
2000 – 2009
- 2009
- [p1]Sandro Bartolini, Roberto Giorgi, Enrico Martinelli:
Instruction Set Extensions for Cryptographic Applications. Cryptographic Engineering 2009: 191-233 - [e4]Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete:
Proceedings of the 10th workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '09, Raleigh, North Carolina, USA, September 13, 2009. ACM 2009, ISBN 978-1-60558-830-8 [contents] - 2008
- [j10]Sandro Bartolini, Irina Branovic, Roberto Giorgi
Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2m). IEEE Trans. Computers 57(5): 672-685 (2008) - [c4]Timothy M. Jones
Instruction Cache Energy Saving Through Compiler Way-Placement. DATE 2008: 1196-1201 - [e3]Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, Roberto Giorgi:
Proceedings of the 9th workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '08, Toronto, Canada, October 26, 2008. ACM 2008, ISBN 978-1-60558-243-6 [contents] - 2007
- [j9]Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete:
MEmory performance: DEaling with applications, systems and architecture. SIGARCH Comput. Archit. News 35(4): 4-5 (2007) - [c3]Sandro Bartolini, Cinzia Castagnini, Enrico Martinelli:
Inclusion of a Montgomery Multiplier Unit into an Embedded Processor's Datapath to Speed-up Elliptic Curve Cryptography. IAS 2007: 95-100 - [e2]Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, Roberto Giorgi:
Proceedings of the 2007 workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '07, Brasov, Romania, September 16, 2007. ACM 2007, ISBN 978-1-59593-807-7 [contents] - 2006
- [j8]Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete:
Embedded processors and systems: Architectural issues and solutions for emerging applications. J. Embed. Comput. 2(1): 1-3 (2006) - [j7]Sandro Bartolini, Roberto Giorgi:
Issues in Embedded Single-Chip Multicore Architectures. J. Embed. Comput. 2(2): 137-139 (2006) - [j6]Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete:
Memory performance: dealing with applications, systems and architecture. SIGARCH Comput. Archit. News 34(1): 1-2 (2006) - 2005
- [j5]Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete:
Guests editor's introduction. SIGARCH Comput. Archit. News 33(3): 1-2 (2005) - [j4]Sandro Bartolini, Cosimo Antonio Prete:
Optimizing instruction cache performance of embedded systems. ACM Trans. Embed. Comput. Syst. 4(4): 934-965 (2005) - 2004
- [j3]Sandro Bartolini, Cosimo Antonio Prete:
A proposal for input-sensitivity analysis of profile-driven optimizations on embedded applications. SIGARCH Comput. Archit. News 32(3): 70-77 (2004) - [c2]Sandro Bartolini, Irina Branovic, Roberto Giorgi
A Performance Evaluation of ARM ISA Extension for Elliptic Curve Cryptography over Binary Finite Fields. SBAC-PAD 2004: 238-245 - [e1]Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete:
Proceedings of the 2004 workshop on MEmory performance - DEaling with Applications , systems and architecture, MEDEA '04, Antibes Juan-les-Pins, France, September 29 - October 3, 2004. ACM 2004 [contents] - 2002
- [j2]Sandro Bartolini, Cosimo Antonio Prete:
A cache-aware program transformation technique suitable for embedded systems. Inf. Softw. Technol. 44(13): 783-795 (2002) - 2001
- [j1]Sandro Bartolini, Roberto Giorgi, Jelica Protic, Cosimo Antonio Prete, Mateo Valero:
Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction. SIGARCH Comput. Archit. News 29(5): 9-12 (2001) - [c1]Sandro Bartolini, Cosimo Antonio Prete:
An Object Level Transformation Technique to Improve the Performance of Embedded Applications. SCAM 2001: 26-34
Coauthor Index
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last updated on 2024-06-10 20:27 CEST by the dblp team
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