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Sayeef S. Salahuddin
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2020 – today
- 2024
- [i6]Saavan Patel, Philip Canoza, Adhiraj Datar, Steven Lu, Chirag Garg, Sayeef S. Salahuddin:
PASS: An Asynchronous Probabilistic Processor for Next Generation Intelligence. CoRR abs/2409.10325 (2024) - 2023
- [j8]Prabhat Kumar
, Andrew Nonaka, Revathi Jambunathan
FerroX: A GPU-accelerated, 3D phase-field simulation framework for modeling ferroelectric devices. Comput. Phys. Commun. 290: 108757 (2023) - [c14]Li-Chen Wang, W. Li, Nirmaan Shanker, Suraj S. Cheema, Shang-Lin Hsu, S. Volkman, U. Sikder, C. Garg, J.-H. Park, Y.-H. Liao, Yen-Kai Lin, Chenming Hu, Sayeef S. Salahuddin:
Record Transconductance in Leff~30 nm Self-Aligned Replacement Gate ETSOI nFETs Using Low EOT Negative Capacitance HfO2-ZrO2 Superlattice Gate Stack. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c13]Chetan K. Dabhi, Girish Pahwa
Compact Model for Trap Assisted Tunneling based GIDL. DRC 2022: 1-2 - [c12]Nirmaan Shanker, Li-Chen Wang, Suraj S. Cheema, Wenshen Li, Nilotpal Choudhury, Chenming Hu, Souvik Mahapatra, Sayeef S. Salahuddin:
On the PBTI Reliability of Low EOT Negative Capacitance 1.8 nm HfO2-ZrO2 Superlattice Gate Stack on Lg=90 nm nFETs. VLSI Technology and Circuits 2022: 421-422 - [i5]Richard A. Gottscho, Edlyn V. Levine, Tsu-Jae King Liu, Paul C. McIntyre, Subhasish Mitra, Boris Murmann, Jan M. Rabaey, Sayeef S. Salahuddin, Willy C. Shih, H.-S. Philip Wong:
Innovating at Speed and at Scale: A Next Generation Infrastructure for Accelerating Semiconductor Technologies. CoRR abs/2204.02216 (2022) - [i4]Prabhat Kumar, Andrew Nonaka, Revathi Jambunathan, Girish Pahwa
FerroX : A GPU-accelerated, 3D Phase-Field Simulation Framework for Modeling Ferroelectric Devices. CoRR abs/2210.15668 (2022) - 2021
- [c11]Sayeef S. Salahuddin:
Ultrathin Ferroelectricity and Its Application in Advanced Logic and Memory Devices. IRPS 2021: 1-4 - 2020
- [j7]H.-S. Philip Wong
A Density Metric for Semiconductor Technology [Point of View]. Proc. IEEE 108(4): 478-482 (2020) - [j6]H.-S. Philip Wong, Kerem Akarvardar, Dimitri A. Antoniadis, Jeffrey Bokor, Chenming Hu, Tsu-Jae King Liu, Subhasish Mitra, James D. Plummer, Sayeef S. Salahuddin, Lei Deng, Xin-Guo Li, Song Han, Luping Shi, Yuan Xie, Elias Yaacoub, Mohamed-Slim Alouini, Ahmed Douik, Hayssam Dahrouj, Tareq Y. Al-Naffouri:
Scanning the Issue. Proc. IEEE 108(4): 483-484 (2020) - [c10]Ava J. Tan, Li-Chen Wang, Yu-Hung Liao, Jong-Ho Bae, Chenming Hu, Sayeef S. Salahuddin:
Reliability of Ferroelectric HfO2-based Memories: From MOS Capacitor to FeFET. DRC 2020: 1-2 - [c9]Ramin Rajaei, Yen-Kai Lin, Sayeef S. Salahuddin, Michael T. Niemier, Xiaobo Sharon Hu
Dynamic Memory and Sequential Logic Design using Negative Capacitance FinFETs. ISCAS 2020: 1-5 - [c8]Ramin Rajaei, Yen-Kai Lin, Sayeef S. Salahuddin, Michael T. Niemier, Xiaobo Sharon Hu
GC-eDRAM design using hybrid FinFET/NC-FinFET. ISLPED 2020: 199-204 - [i3]Saavan Patel, Philip Canoza, Sayeef S. Salahuddin:
Logically Synthesized, Hardware-Accelerated, Restricted Boltzmann Machines for Combinatorial Optimization and Integer Factorization. CoRR abs/2007.13489 (2020) - [i2]Saavan Patel, Lili Chen, Philip Canoza, Sayeef S. Salahuddin:
Ising Model Optimization Problems on a FPGA Accelerated Restricted Boltzmann Machine. CoRR abs/2008.04436 (2020)
2010 – 2019
- 2019
- [j5]Justin C. Wong, Sayeef S. Salahuddin
Negative Capacitance Transistors. Proc. IEEE 107(1): 49-62 (2019) - [i1]Saavan Patel, Sayeef S. Salahuddin:
Combining Learned Representations for Combinatorial Optimization. CoRR abs/1909.03978 (2019) - 2017
- [c7]Suman Datta
In Quest of the Next Information Processing Substrate: Extended Abstract: Invited. DAC 2017: 17:1-17:6 - [c6]Sandeep Kumar Samal, Sourabh Khandelwal
Full chip power benefits with negative capacitance FETs. ISLPED 2017: 1-6 - 2016
- [c5]Sumitha George, Kaisheng Ma
Nonvolatile memory design based on ferroelectric FETs. DAC 2016: 118:1-118:6 - 2013
- [j4]Subho Chatterjee, Sayeef S. Salahuddin, Satish Kumar, Saibal Mukhopadhyay:
Electrothermal analysis of spin-transfer-torque random access memory arrays. ACM J. Emerg. Technol. Comput. Syst. 9(2): 15:1-15:17 (2013) - 2011
- [c4]Youngki Yoon, Sayeef S. Salahuddin:
Performance assessment of partially unzipped carbon nanotube field-effect transistors. NANOARCH 2011: 157-161 - 2010
- [j3]Subho Chatterjee, Sayeef S. Salahuddin, Saibal Mukhopadhyay:
Dual-Source-Line-Bias Scheme to Improve the Read Margin and Sensing Accuracy of STTRAM in Sub-90-nm Nodes. IEEE Trans. Circuits Syst. II Express Briefs 57-II(3): 208-212 (2010) - [j2]Jing Li
Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective. IEEE Trans. Very Large Scale Integr. Syst. 18(12): 1710-1723 (2010) - [c3]Subho Chatterjee, Sayeef S. Salahuddin, Satish Kumar, Saibal Mukhopadhyay:
Analysis of thermal behaviors of spin-torque-transfer RAM: a simulation study. ISLPED 2010: 13-18
2000 – 2009
- 2008
- [c2]Jing Li
Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement. CICC 2008: 193-196 - [c1]Jing Li
Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement. DAC 2008: 278-283 - 2004
- [j1]Md. Kamrul Hasan, Sayeef S. Salahuddin, M. Rezwan Khan:
Reducing signal-bias from MAD estimated noise level for DCT speech enhancement. Signal Process. 84(1): 151-162 (2004)
Coauthor Index
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