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Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement

Published: 08 June 2008 Publication History

Abstract

Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future universal memory. It combines the desirable attributes of current memory technologies such as SRAM, DRAM and flash memories. It also solves the key drawbacks of conventional MRAM technology: poor scalability and high write current. In this paper, we analyzed and modeled the failure probabilities of STT MRAM cells due to parameter variations. Based on the model, we developed an efficient simulation tool to capture the coupled electro/magnetic dynamics of spintronic device, leading to effective prediction for memory yield. We also developed a statistical optimization methodology to minimize the memory failure probability. The proposed methodology can be used at an early stage of the design cycle to enhance memory yield.

References

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A. D. Smith et al. STT-RAM --A New Spin on Universal Memory, Future Fab Intl. Vol. 23, July 2007
[2]
S. Tehrani et al., Magnetoresistive Random Access Memory Using Magnetic Tunnel Junctions, Proceeding of The IEEE, Vol. 91, No. 5, May 2003
[3]
E. Y. Chen et al., Comparison of oxidation methods for magnetic tunnel junction material, J. Appl. Phys., vol. 87, pp. 6061--6063, 2000.
[4]
S. Mukhopadhyay et al., Modeling of Failure Probability and Statistical Design of SRAM Array for Yield Enhancement in Nanoscaled CMOS, TCAD, pp 1859--1880, Dec. 2005.
[5]
M. Hosomi et al., A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching: Spin-RAM, IEDM Tech. Dig., pp. 473--476, Dec., 2006.
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S. Salahuddin et al., Quantum Transport Simulation of Tunneling Based Spin Torque Transfer (STT) Devices: Design Trade offs and Torque Efficiency, IEDM Tech. Dig., pp. 121--124, Dec., 2007.
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A. R. Alvarez et al., Application of statistical design and response surface methods to computer-aided VLSI device design, TCAD, pp. 272--288, Feb. 1988.
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  • (2023)A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-FlopsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.323779431:4(532-542)Online publication date: Apr-2023
  • (2023)Process-induced magnetic tunnel junction damage and its recovery for the development of spin–orbit torque magnetic random access memoryJournal of Magnetism and Magnetic Materials10.1016/j.jmmm.2022.170296565(170296)Online publication date: Jan-2023
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  1. Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement

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    cover image ACM Conferences
    DAC '08: Proceedings of the 45th annual Design Automation Conference
    June 2008
    993 pages
    ISBN:9781605581156
    DOI:10.1145/1391469
    • General Chair:
    • Limor Fix
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 08 June 2008

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    Author Tags

    1. STT MRAM
    2. yield

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    • (2024)A Non-Volatile Flip-Flop Circuit Using One MTJ and Reference Resistance2024 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC)10.1109/ITC-CSCC62988.2024.10628353(1-6)Online publication date: 2-Jul-2024
    • (2023)A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-FlopsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.323779431:4(532-542)Online publication date: Apr-2023
    • (2023)Process-induced magnetic tunnel junction damage and its recovery for the development of spin–orbit torque magnetic random access memoryJournal of Magnetism and Magnetic Materials10.1016/j.jmmm.2022.170296565(170296)Online publication date: Jan-2023
    • (2022)Integration of high-performance spin-orbit torque MRAM devices by 200-mm-wafer manufacturing platformJournal of Semiconductors10.1088/1674-4926/43/10/10250143:10(102501)Online publication date: 1-Oct-2022
    • (2021)High-Performance Computing-in-Memory Architecture Using STT-/SOT-Based Series Triple-Level Cell MRAMIEEE Transactions on Magnetics10.1109/TMAG.2021.308486957:8(1-12)Online publication date: Aug-2021
    • (2021)High-Performance Computing-in-Memory Architecture Based on Single-Level and Multilevel Cell Differential Spin Hall MRAMIEEE Transactions on Magnetics10.1109/TMAG.2021.306937257:9(1-15)Online publication date: Sep-2021
    • (2021)Ultra-Efficient Nonvolatile Approximate Full-Adder with Spin-Hall Assisted MTJ Cells for In-Memory Computing ApplicationsIEEE Transactions on Magnetics10.1109/TMAG.2021.3064224(1-1)Online publication date: 2021
    • (2021)Magnetoresistive Circuits and Systems: Embedded Non-Volatile Memory to Crossbar ArraysIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2021.306968268:6(2281-2294)Online publication date: Jun-2021
    • (2021)SpinSim: A Computer Architecture-Level Variation Aware STT-MRAM Performance Evaluation Framework2021 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS51556.2021.9401359(1-5)Online publication date: May-2021
    • (2020)Energy-Efficient Differential Spin Hall MRAM-Based 4-2 Magnetic CompressorIEEE Transactions on Magnetics10.1109/TMAG.2019.294058156:1(1-11)Online publication date: Jan-2020
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