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Koichiro Mashiko
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2010 – 2019
- 2019
- [c4]Pyi Phyo Aung
, Koichiro Mashiko, Nordinah Binti Ismail, Chia Yee Ooi:
Evaluation of SRAM PUF Characteristics and Generation of Stable Bits for IoT Security. IRICT 2019: 441-450
2000 – 2009
- 2007
- [j16]Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada:
A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm. IEICE Trans. Electron. 90-C(6): 1181-1188 (2007) - 2006
- [j15]Hao San, Akira Hayakawa, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Kazuyuki Kobayashi, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada:
Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 908-915 (2006) - [j14]Masafumi Uemori, Haruo Kobayashi, Tomonari Ichikawa, Atsushi Wada, Koichiro Mashiko, Toshiro Tsukada, Masao Hotta:
High-Speed Continuous-Time Subsampling Bandpass DeltaSigmaAD Modulator Architecture Employing Radio Frequency DAC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 916-923 (2006) - 2000
- [j13]Toru Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara:
A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology. IEEE J. Solid State Circuits 35(5): 751-756 (2000)
1990 – 1999
- 1997
- [j12]Vojin G. Oklobdzija, Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi:
Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]. IEEE J. Solid State Circuits 32(2): 292 (1997) - [j11]Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko:
Authors Reply. IEEE J. Solid State Circuits 32(2): 293 (1997) - [c3]Hiroaki Suzuki, Hiroshi Makino, Koichiro Mashiko, Hisanori Hamano:
A Floating Point Divider using Redundant Binary Circuits and an Asynchronous Clock Scheme. ICCD 1997: 685-689 - 1996
- [j10]Kimio Ueda, Nagisa Sasaki, Hisayasu Sato, Koichiro Mashiko:
A fully compensated active pull-down ECL circuit with self-adjusting driving capability. IEEE J. Solid State Circuits 31(1): 46-53 (1996) - [j9]Hiroshi Makino, Hiroaki Suzuki, Hiroyuki Morinaka, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi:
A 286 MHz 64-b floating point multiplier with enhanced CG operation. IEEE J. Solid State Circuits 31(4): 504-513 (1996) - [j8]Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko:
An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture. IEEE J. Solid State Circuits 31(6): 773-783 (1996) - [j7]Kiniio Ueda, Hiroaki Suzuki, Kakutaro Suda, Hirofumi Shinohara, Koichiro Mashiko:
A 64-bit carry look ahead adder using pass transistor BiCMOS gates. IEEE J. Solid State Circuits 31(6): 810-818 (1996) - [j6]Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi:
Leading-zero anticipatory logic for high-speed floating point addition. IEEE J. Solid State Circuits 31(8): 1157-1164 (1996) - [j5]Hisayasu Sato, Kenichi Kashiwagi, Kazuhito Niwano, Tetsuya Iga, Tatsuhiko Ikeda, Koichiro Mashiko, Tadashi Sumi, Koji Tsuchihashi:
A 1.9-GHz single chip IF transceiver for digital cordless phones. IEEE J. Solid State Circuits 31(12): 1974-1980 (1996) - [c2]Koichiro Mashiko:
How to design low-power digital cellular phones. ISLPED 1996: 177-180 - 1995
- [j4]Yasunobu Nakase, Hiroaki Suzuki, Hiroshi Makino, Hirofumi Shinohara, Koichiro Mashiko:
A BiCMOS wired-OR logic. IEEE J. Solid State Circuits 30(6): 622-628 (1995) - 1994
- [j3]Hisayasu Sato, Kimio Ueda, Nagisa Sasaki, Tatsuhiko Ikeda, Koichiro Mashiko:
A voltage compensated series-gate bipolar circuit operating at sub-2 V. IEEE J. Solid State Circuits 29(10): 1200-1205 (1994) - 1990
- [j2]Kazutami Arimoto, Yoshio Matsuda, Kiyohiro Furutani, Masaki Tsukude, Tsukasa Ooishi, Koichiro Mashiko, Kuzuyasu Fujishima:
A speed-enhanced DRAM array architecture with embedded ECC. IEEE J. Solid State Circuits 25(1): 11-17 (1990)
1980 – 1989
- 1989
- [j1]Kiyohiro Furutani, Kazutami Arimoto, Hiroshi Miyamoto, Toshifumi Kobayashi, Kenichi Yasuda, Koichiro Mashiko:
A built-in Hamming code ECC circuit for DRAMs. IEEE J. Solid State Circuits 24(1): 50-56 (1989) - 1985
- [c1]Hiroshi Miyamoto, Koichiro Mashiko, Yoshikazu Morooka, Kazutami Arimoto, Michihiro Yamada, Takao Nakano:
Test Pattern Considerations for Fault Tolerant High Density DRAM. ITC 1985: 451-455
Coauthor Index
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