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Jae-Seok Yang
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2010 – 2019
- 2013
- [j2]Krit Athikulwongse, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim
:
Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(6): 905-917 (2013) - 2012
- [c12]David Z. Pan, Sung Kyu Lim
Design for manufacturability and reliability for TSV-based 3D ICs. ASP-DAC 2012: 750-755 - [c11]Bei Yu, Jhih-Rong Gao, Duo Ding, Yongchan Ban, Jae-Seok Yang, Kun Yuan, Minsik Cho, David Z. Pan:
Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper). ICCAD 2012: 240-242 - 2011
- [c10]Jae-Seok Yang, Jiwoo Pak, Xin Zhao, Sung Kyu Lim
Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs. ASP-DAC 2011: 621-626 - [c9]Yongchan Ban, Jae-Seok Yang:
Layout aware line-edge roughness modeling and poly optimization for leakage minimization. DAC 2011: 447-452 - [c8]Wooyoung Jang, Ou He, Jae-Seok Yang, David Z. Pan:
Chemical-mechanical polishing aware application-specific 3D NoC design. ICCAD 2011: 207-212 - 2010
- [j1]Kun Yuan, Jae-Seok Yang, David Z. Pan:
Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 185-196 (2010) - [c7]Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, David Z. Pan:
A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography. ASP-DAC 2010: 637-644 - [c6]Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim
TSV stress aware timing analysis with applications to 3D-IC layout optimization. DAC 2010: 803-806 - [c5]Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim
Stress-driven 3D-IC placement with TSV keep-out zone and regularity study. ICCAD 2010: 669-674
2000 – 2009
- 2009
- [c4]Kun Yuan, Jae-Seok Yang, David Z. Pan:
Double patterning layout decomposition for simultaneous conflict and stitch minimization. ISPD 2009: 107-114 - 2008
- [c3]Jae-Seok Yang, David Z. Pan:
Overlay aware interconnect and timing variation modeling for double patterning technology. ICCAD 2008: 488-493 - [c2]Jae-Seok Yang, Andrew R. Neureuther:
Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner. ISQED 2008: 352-356 - 2003
- [c1]Jae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-Hyun Yoo, Jeong-Taek Kong:
Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis. ISQED 2003: 344-347
Coauthor Index
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