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Chao-Hsun Chen
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2020 – today
- 2022
- [c8]Kuan-Hsun Duh, Cheng-Wen Wu
, Ming-Der Shieh, Chao-Hsun Chen, Ming-Yan Fan:
Aging Impact of Power MOSFETs in Charger with Different Operation Frequency. ATS 2022: 54-59 - [c7]Yu-You Chou, Cheng-Wen Wu
Battery Pack Reliability and Endurance Enhancement for Electric Vehicles by Dynamic Reconfiguration. ATS 2022: 66-71
2010 – 2019
- 2015
- [c6]Chi-Chun Yang, Jin-Fu Li, Yun-Chao Yu, Kuan-Te Wu, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou:
A hybrid built-in self-test scheme for DRAMs. VLSI-DAT 2015: 1-4 - 2014
- [c5]Yun-Chao You, Chi-Chun Yang, Jin-Fu Li, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs. ATS 2014: 1-6 - 2013
- [j5]Po-Yuan Chen, Chin-Lung Su, Chao-Hsun Chen, Cheng-Wen Wu
Generalization of an Enhanced ECC Methodology for Low Power PSRAM. IEEE Trans. Computers 62(7): 1318-1331 (2013) - 2010
- [j4]Yu-Tsao Hsing
Economic Analysis of the HOY Wireless Test Methodology. IEEE Des. Test Comput. 27(3): 20-30 (2010) - [j3]Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu
Built-In Self-Repair Schemes for Flash Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(8): 1243-1256 (2010)
2000 – 2009
- 2008
- [j2]Jen-Chieh Yeh, Chao-Hsun Chen, Cheng-Wen Wu
A Systematic Approach to Memory Test Time Reduction. IEEE Des. Test Comput. 25(6): 560-570 (2008) - 2007
- [j1]Rei-Fu Huang, Chao-Hsun Chen, Cheng-Wen Wu
Economic Aspects of Memory Built-in Self-Repair. IEEE Des. Test Comput. 24(2): 164-172 (2007) - 2006
- [c4]Po-Yuan Chen, Yi-Ting Yeh, Chao-Hsun Chen, Jen-Chieh Yeh, Cheng-Wen Wu
An Enhanced EDAC Methodology for Low Power PSRAM. ITC 2006: 1-10 - [c3]Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu
A Built-In Self-Repair Scheme for NOR-Type Flash Memory. VTS 2006: 114-119 - 2005
- [c2]Yu-Chun Dawn, Jen-Chieh Yeh, Cheng-Wen Wu
Flash Memory Die Sort by a Sample Classification Method. Asian Test Symposium 2005: 182-187 - [c1]Jen-Chieh Yeh, Shyr-Fen Kuo, Cheng-Wen Wu
A systematic approach to reducing semiconductor memory test time in mass production. MTDT 2005: 97-102
Coauthor Index
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