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Vivienne Sze
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- affiliation: Massachusetts Institute of Technology, MA, USA
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2020 – today
- 2024
- [j28]Peter Zhi Xuan Li
, Sertac Karaman
GMMap: Memory-Efficient Continuous Occupancy Map Using Gaussian Mixture Model. IEEE Trans. Robotics 40: 1339-1355 (2024) - [c60]Tanner Andrulis, Joel S. Emer, Vivienne Sze:
CiMLoop: A Flexible, Accurate, and Fast Compute-In-Memory Modeling Tool. ISPASS 2024: 10-23 - [c59]Tanner Andrulis, Gohar Irfan Chaudhry, Vinith M. Suriyakumar, Joel S. Emer, Vivienne Sze:
Architecture-Level Modeling of Photonic Deep Neural Network Accelerators. ISPASS 2024: 307-309 - [c58]Vibhaalakshmi Sivaraman, Pantea Karimi, Vedantha Venkatapathy, Mehrdad Khani Shirkoohi, Sadjad Fouladi, Mohammad Alizadeh, Frédo Durand, Vivienne Sze:
Gemino: Practical and Robust Neural Compression for Video Conferencing. NSDI 2024: 569-590 - [i32]Tanner Andrulis, Ruicong Chen, Hae-Seung Lee, Joel S. Emer, Vivienne Sze:
Modeling Analog-Digital-Converter Energy and Area for Compute-In-Memory Accelerator Design. CoRR abs/2404.06553 (2024) - [i31]Tanner Andrulis, Joel S. Emer, Vivienne Sze:
CiMLoop: A Flexible, Accurate, and Fast Compute-In-Memory Modeling Tool. CoRR abs/2405.07259 (2024) - [i30]Tanner Andrulis, Gohar Irfan Chaudhry, Vinith M. Suriyakumar, Joel S. Emer, Vivienne Sze:
Architecture-Level Modeling of Photonic Deep Neural Network Accelerators. CoRR abs/2405.07266 (2024) - [i29]Dasong Gao, Peter Zhi Xuan Li, Vivienne Sze, Sertac Karaman:
GEVO: Memory-Efficient Monocular Visual Odometry Using Gaussians. CoRR abs/2409.09295 (2024) - [i28]Michael Gilbert, Yannan Nellie Wu, Joel S. Emer, Vivienne Sze:
LoopTree: Exploring the Fused-layer Dataflow Accelerator Design Space. CoRR abs/2409.13625 (2024) - [i27]Zih-Sing Fu, Soumya Sudhakar, Sertac Karaman, Vivienne Sze:
DecTrain: Deciding When to Train a DNN Online. CoRR abs/2410.02980 (2024) - 2023
- [j27]Vivienne Sze:
Unleashing the Power of Deep Learning. Commun. ACM 66(7): 10-11 (2023) - [j26]Hsin-Yu Lai
Individualized Tracking of Neurocognitive-State-Dependent Eye-Movement Features Using Mobile Devices. Proc. ACM Interact. Mob. Wearable Ubiquitous Technol. 7(1): 19:1-19:23 (2023) - [j25]Soumya Sudhakar
Data Centers on Wheels: Emissions From Computing Onboard Autonomous Vehicles. IEEE Micro 43(1): 29-39 (2023) - [c57]Tanner Andrulis
RAELLA: Reforming the Arithmetic for Efficient, Low-Resolution, and Low-Loss Analog PIM: No Retraining Required! ISCA 2023: 27:1-27:16 - [c56]Michael Gilbert, Yannan Nellie Wu, Angshuman Parashar, Vivienne Sze, Joel S. Emer:
LoopTree: Enabling Exploration of Fused-layer Dataflow Accelerators. ISPASS 2023: 316-318 - [c55]Yannan Nellie Wu
HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity. MICRO 2023: 1106-1120 - [c54]Zi Yu Xue
Tailors: Accelerating Sparse Tensor Algebra by Overbooking Buffer Capacity. MICRO 2023: 1347-1363 - [i26]Tanner Andrulis, Joel S. Emer, Vivienne Sze:
RAELLA: Reforming the Arithmetic for Efficient, Low-Resolution, and Low-Loss Analog PIM: No Retraining Required! CoRR abs/2304.07935 (2023) - [i25]Yannan Nellie Wu, Po-An Tsai, Saurav Muralidharan, Angshuman Parashar, Vivienne Sze, Joel S. Emer:
HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity. CoRR abs/2305.12718 (2023) - [i24]Peter Zhi Xuan Li, Sertac Karaman, Vivienne Sze:
GMMap: Memory-Efficient Continuous Occupancy Map Using Gaussian Mixture Model. CoRR abs/2306.03740 (2023) - [i23]Zi Yu Xue, Yannan Nellie Wu, Joel S. Emer, Vivienne Sze:
Tailors: Accelerating Sparse Tensor Algebra by Overbooking Buffer Capacity. CoRR abs/2310.00192 (2023) - 2022
- [j24]Hsin-Yu Lai
App-Based Saccade Latency and Directional Error Determination Across the Adult Age Spectrum. IEEE Trans. Biomed. Eng. 69(2): 1029-1039 (2022) - [c53]Peter Zhi Xuan Li
Memory-Efficient Gaussian Fitting for Depth Images in Real Time. ICRA 2022: 8003-8009 - [c52]Soumya Sudhakar, Vivienne Sze, Sertac Karaman:
Uncertainty from Motion for DNN Monocular Depth Estimation. ICRA 2022: 8673-8679 - [c51]Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer:
Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling. MICRO 2022: 1377-1395 - [i22]Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer:
Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling. CoRR abs/2205.05826 (2022) - [i21]Vijay Gadepally, Gregory Angelides, Andrei Barbu, Andrew Bowne, Laura J. Brattain, Tamara Broderick
Developing a Series of AI Challenges for the United States Department of the Air Force. CoRR abs/2207.07033 (2022) - [i20]Vibhaalakshmi Sivaraman, Pantea Karimi, Vedantha Venkatapathy, Mehrdad Khani Shirkoohi, Sadjad Fouladi, Mohammad Alizadeh, Frédo Durand, Vivienne Sze:
Gemino: Practical and Robust Neural Compression for Video Conferencing. CoRR abs/2209.10507 (2022) - [i19]Keshav Gupta, Peter Zhi Xuan Li, Sertac Karaman, Vivienne Sze:
Efficient Computation of Map-scale Continuous Mutual Information on Chip in Real Time. CoRR abs/2210.03623 (2022) - 2021
- [c50]Tien-Ju Yang, Yi-Lun Liao, Vivienne Sze:
NetAdaptV2: Efficient Neural Architecture Search With Fast Super-Network Training and Architecture Optimization. CVPR 2021: 2402-2411 - [c49]Jessica Ray, Ajay Brahmakshatriya, Richard Wang, Shoaib Kamil, Albert Reuther, Vivienne Sze, Saman P. Amarasinghe
Domain-Specific Language Abstractions for Compression. DCC 2021: 364 - [c48]Keshav Gupta
Efficient Computation of Map-scale Continuous Mutual Information on Chip in Real Time. IROS 2021: 6464-6470 - [c47]Francis Wang, Yannan Nellie Wu, Matthew E. Woicik, Joel S. Emer, Vivienne Sze:
Architecture-Level Energy Estimation for Heterogeneous Computing Systems. ISPASS 2021: 229-231 - [c46]Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer:
Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators. ISPASS 2021: 232-234 - [c45]Sukhwan Lim, Luca Benini, Vivienne Sze:
Session 9 Overview: ML Processors From Cloud to Edge Machine Learning Subcommittee. ISSCC 2021: 142-143 - [c44]Negar Reiskarimian
SE4: ICs in PandemICs. ISSCC 2021: 543-545 - [i18]Tien-Ju Yang, Yi-Lun Liao, Vivienne Sze:
NetAdaptV2: Efficient Neural Architecture Search with Fast Super-Network Training and Architecture Optimization. CoRR abs/2104.00031 (2021) - [i17]Yi-Lun Liao, Sertac Karaman, Vivienne Sze:
Searching for Efficient Multi-Stage Vision Transformers. CoRR abs/2109.00642 (2021) - 2020
- [b2]Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, Joel S. Emer:
Efficient Processing of Deep Neural Networks. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2020, ISBN 978-3-031-00638-8 - [j23]Zhengdong Zhang
FSMI: Fast computation of Shannon mutual information for information-theoretic mapping. Int. J. Robotics Res. 39(9) (2020) - [j22]James Noraky
Low Power Depth Estimation of Rigid Objects for Time-of-Flight Imaging. IEEE Trans. Circuits Syst. Video Technol. 30(6): 1524-1534 (2020) - [j21]Hsin-Yu Lai
Measuring Saccade Latency Using Smartphone Cameras. IEEE J. Biomed. Health Informatics 24(3): 885-897 (2020) - [c43]Soumya Sudhakar, Sertac Karaman, Vivienne Sze:
Balancing Actuation and Computing Energy in Motion Planning. ICRA 2020: 4259-4265 - [c42]Theia Henderson, Vivienne Sze, Sertac Karaman:
An Efficient and Continuous Approach to Information-Theoretic Exploration. ICRA 2020: 8566-8572 - [c41]Yannan Nellie Wu, Vivienne Sze, Joel S. Emer:
An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs. ISPASS 2020: 116-118 - [c40]Vivienne Sze:
Efficient Computing for AI and Robotics. VLSI-DAT 2020: 1 - [e2]Inderjit S. Dhillon, Dimitris S. Papailiopoulos, Vivienne Sze:
Proceedings of the Third Conference on Machine Learning and Systems, MLSys 2020, Austin, TX, USA, March 2-4, 2020. mlsys.org 2020 [contents] - [i16]James Noraky, Vivienne Sze:
Depth Map Estimation of Dynamic Scenes Using Prior Depth Information. CoRR abs/2002.00297 (2020) - [i15]Liane Bernstein, Alexander Sludds, Ryan Hamerly, Vivienne Sze, Joel S. Emer, Dirk R. Englund:
Freely scalable and reconfigurable optical hardware for deep learning. CoRR abs/2006.13926 (2020)
2010 – 2019
- 2019
- [j20]Yu-Hsin Chen
Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(2): 292-308 (2019) - [j19]Amr Suleiman
Navion: A 2-mW Fully Integrated Real-Time Visual-Inertial Odometry Accelerator for Autonomous Navigation of Nano Drones. IEEE J. Solid State Circuits 54(4): 1106-1119 (2019) - [c39]Yannan Nellie Wu, Joel S. Emer, Vivienne Sze:
Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs. ICCAD 2019: 1-8 - [c38]James Noraky, Charles Mathy, Alan Cheng, Vivienne Sze:
Low Power Adaptive Time-of-Flight Imaging for Multiple Rigid Objects. ICIP 2019: 3517-3521 - [c37]Diana Wofk, Fangchang Ma, Tien-Ju Yang, Sertac Karaman, Vivienne Sze:
FastDepth: Fast Monocular Depth Estimation on Embedded Systems. ICRA 2019: 6101-6108 - [c36]Zhengdong Zhang, Trevor Henderson, Vivienne Sze, Sertac Karaman:
FSMI: Fast Computation of Shannon Mutual Information for Information-Theoretic Mapping. ICRA 2019: 6912-6918 - [c35]Peter Zhi Xuan Li
High-Throughput Computation of Shannon Mutual Information on Chip. Robotics: Science and Systems 2019 - [i14]Tien-Ju Yang, Maxwell D. Collins, Yukun Zhu, Jyh-Jing Hwang, Ting Liu, Xiao Zhang, Vivienne Sze, George Papandreou, Liang-Chieh Chen:
DeeperLab: Single-Shot Image Parser. CoRR abs/1902.05093 (2019) - [i13]Diana Wofk, Fangchang Ma, Tien-Ju Yang, Sertac Karaman, Vivienne Sze:
FastDepth: Fast Monocular Depth Estimation on Embedded Systems. CoRR abs/1903.03273 (2019) - [i12]Alexander Ratner, Dan Alistarh, Gustavo Alonso, David G. Andersen, Peter Bailis, Sarah Bird, Nicholas Carlini, Bryan Catanzaro, Eric S. Chung, Bill Dally, Jeff Dean, Inderjit S. Dhillon, Alexandros G. Dimakis, Pradeep Dubey, Charles Elkan, Grigori Fursin, Gregory R. Ganger, Lise Getoor, Phillip B. Gibbons, Garth A. Gibson, Joseph E. Gonzalez, Justin Gottschlich, Song Han, Kim M. Hazelwood, Furong Huang, Martin Jaggi, Kevin G. Jamieson, Michael I. Jordan, Gauri Joshi, Rania Khalaf, Jason Knight, Jakub Konecný, Tim Kraska, Arun Kumar, Anastasios Kyrillidis, Jing Li
SysML: The New Frontier of Machine Learning Systems. CoRR abs/1904.03257 (2019) - [i11]Zhengdong Zhang, Trevor Henderson, Sertac Karaman, Vivienne Sze:
FSMI: Fast computation of Shannon Mutual Information for information-theoretic mapping. CoRR abs/1905.02238 (2019) - [i10]Tien-Ju Yang, Vivienne Sze:
Design Considerations for Efficient Deep Neural Networks on Processing-in-Memory Accelerators. CoRR abs/1912.12167 (2019) - 2018
- [j18]Mehul Tikekar, Vivienne Sze
A Fully Integrated Energy-Efficient H.265/HEVC Decoder With eDRAM for Wearable Devices. IEEE J. Solid State Circuits 53(8): 2368-2377 (2018) - [c34]Vivienne Sze, Yu-Hsin Chen, Joel S. Emer, Amr Suleiman, Zhengdong Zhang:
Hardware for machine learning: Challenges and opportunities. CICC 2018: 1-8 - [c33]Tien-Ju Yang
NetAdapt: Platform-Aware Neural Network Adaptation for Mobile Applications. ECCV (10) 2018: 289-304 - [c32]Gladynel Saavedra-Peña, Hsin-Yu Lai, Vivienne Sze, Thomas Heldt:
Determination of Saccade Latency Distributions using Video Recordings from Consumer-grade Devices. EMBC 2018: 953-956 - [c31]James Noraky, Vivienne Sze:
Depth Estimation of Non-Rigid Objects for Time-Of-Flight Imaging. ICIP 2018: 2925-2929 - [c30]Hsin-Yu Lai, Gladynel Saavedra-Peña, Charles G. Sodini, Thomas Heldt, Vivienne Sze:
Enabling Saccade Latency Measurements with Consumer-Grade Cameras. ICIP 2018: 3169-3173 - [c29]Vivienne Sze, Alison J. Burdett, Sonia Leon, Rikky Muller, Farhana Sheikh, Yildiz Sinangil, Trudy Stetzler, Ingrid Verbauwhede
EE2: Workshop on circuits for social good. ISSCC 2018: 523-525 - [c28]Amr Suleiman, Zhengdong Zhang, Luca Carlone, Sertac Karaman, Vivienne Sze:
Navion: A Fully Integrated Energy-Efficient Visual-Inertial Odometry Accelerator for Autonomous Navigation of Nano Drones. VLSI Circuits 2018: 133-134 - [i9]Tien-Ju Yang, Andrew G. Howard, Bo Chen, Xiao Zhang, Alec Go, Vivienne Sze, Hartwig Adam:
NetAdapt: Platform-Aware Neural Network Adaptation for Mobile Applications. CoRR abs/1804.03230 (2018) - [i8]Yu-Hsin Chen, Joel S. Emer, Vivienne Sze:
Eyeriss v2: A Flexible and High-Performance Accelerator for Emerging Deep Neural Networks. CoRR abs/1807.07928 (2018) - [i7]Amr Suleiman, Zhengdong Zhang, Luca Carlone, Sertac Karaman, Vivienne Sze:
Navion: A 2mW Fully Integrated Real-Time Visual-Inertial Odometry Accelerator for Autonomous Navigation of Nano Drones. CoRR abs/1809.05780 (2018) - 2017
- [j17]Yu-Hsin Chen
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks. IEEE J. Solid State Circuits 52(1): 127-138 (2017) - [j16]Amr Suleiman
A 58.6 mW 30 Frames/s Real-Time Programmable Multiobject Detection Accelerator With Deformable Parts Models on Full HD 1920×1080 Videos. IEEE J. Solid State Circuits 52(3): 844-855 (2017) - [j15]Yu-Hsin Chen, Joel S. Emer, Vivienne Sze:
Using Dataflow to Optimize Energy Efficiency of Deep Neural Network Accelerators. IEEE Micro 37(3): 12-21 (2017) - [j14]Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, Joel S. Emer:
Efficient Processing of Deep Neural Networks: A Tutorial and Survey. Proc. IEEE 105(12): 2295-2329 (2017) - [c27]Tien-Ju Yang, Yu-Hsin Chen, Joel S. Emer, Vivienne Sze:
A method to estimate the energy consumption of deep neural networks. ACSSC 2017: 1916-1920 - [c26]Vivienne Sze, Yu-Hsin Chen, Joel S. Einer, Amr Suleiman, Zhengdong Zhang:
Hardware for machine learning: Challenges and opportunities. CICC 2017: 1-8 - [c25]Zhengdong Zhang, Vivienne Sze:
FAST: A Framework to Accelerate Super-Resolution Processing on Compressed Videos. CVPR Workshops 2017: 1015-1024 - [c24]Tien-Ju Yang, Yu-Hsin Chen, Vivienne Sze:
Designing Energy-Efficient Convolutional Neural Networks Using Energy-Aware Pruning. CVPR 2017: 6071-6079 - [c23]James Noraky, Vivienne Sze:
Low power depth estimation for time-of-flight imaging. ICIP 2017: 2114-2118 - [c22]Amr Suleiman, Yu-Hsin Chen, Joel S. Emer, Vivienne Sze:
Towards closing the energy gap between HOG and CNN features for embedded vision (Invited paper). ISCAS 2017: 1-4 - [c21]Zhengdong Zhang, Amr Suleiman, Luca Carlone, Vivienne Sze, Sertac Karaman:
Visual-Inertial Odometry on Chip: An Algorithm-and-Hardware Co-design Approach. Robotics: Science and Systems 2017 - [i6]Amr Suleiman, Yu-Hsin Chen, Joel S. Emer, Vivienne Sze:
Towards Closing the Energy Gap Between HOG and CNN Features for Embedded Vision. CoRR abs/1703.05853 (2017) - [i5]Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, Joel S. Emer:
Efficient Processing of Deep Neural Networks: A Tutorial and Survey. CoRR abs/1703.09039 (2017) - 2016
- [j13]Jens-Rainer Ohm, Gary J. Sullivan, Vivienne Sze, Thomas Wiegand, Madhukar Budagavi:
Introduction to the Special Issue on HEVC Extensions and Efficient HEVC Implementations. IEEE Trans. Circuits Syst. Video Technol. 26(1): 1-3 (2016) - [j12]Amr Suleiman, Vivienne Sze:
An Energy-Efficient Hardware Implementation of HOG-Based Object Detection at 1080HD 60 fps with Multi-Scale Support. J. Signal Process. Syst. 84(3): 325-337 (2016) - [c20]Yu-Hsin Chen, Joel S. Emer, Vivienne Sze:
Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks. ISCA 2016: 367-379 - [c19]Yu-Hsin Chen, Tushar Krishna, Joel S. Emer, Vivienne Sze:
14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks. ISSCC 2016: 262-263 - [c18]Amr Suleiman, Zhengdong Zhang, Vivienne Sze:
A 58.6mW real-time programmable object detector with multi-scale multi-object support using deformable parts model on 1920×1080 video at 30fps. VLSI Circuits 2016: 1-2 - [i4]Zhengdong Zhang, Vivienne Sze:
FAST: Free Adaptive Super-Resolution via Transfer for Compressed Videos. CoRR abs/1603.08968 (2016) - [i3]Amr Suleiman, Zhengdong Zhang, Vivienne Sze:
A 58.6mW Real-Time Programmable Object Detector with Multi-Scale Multi-Object Support Using Deformable Parts Model on 1920x1080 Video at 30fps. CoRR abs/1607.08635 (2016) - [i2]Tien-Ju Yang, Yu-Hsin Chen, Vivienne Sze:
Designing Energy-Efficient Convolutional Neural Networks using Energy-Aware Pruning. CoRR abs/1611.05128 (2016) - [i1]Vivienne Sze, Yu-Hsin Chen, Joel S. Emer, Amr Suleiman, Zhengdong Zhang:
Hardware for Machine Learning: Challenges and Opportunities. CoRR abs/1612.07625 (2016) - 2015
- [j11]Yu-Hsin Chen
A Deeply Pipelined CABAC Decoder for HEVC Supporting Level 6.2 High-Tier Applications. IEEE Trans. Circuits Syst. Video Technol. 25(5): 856-868 (2015) - [c17]Zhengdong Zhang, Vivienne Sze:
Rotate intra block copy for still image coding. ICIP 2015: 4102-4106 - 2014
- [j10]Mehul Tikekar, Chao-Tsung Huang, Chiraag Juvekar, Vivienne Sze, Anantha P. Chandrakasan:
A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications. IEEE J. Solid State Circuits 49(1): 61-72 (2014) - [c16]Mehul Tikekar, Chao-Tsung Huang, Vivienne Sze, Anantha P. Chandrakasan:
Energy and area-efficient hardware implementation of HEVC inverse transform and dequantization. ICIP 2014: 2100-2104 - [c15]Yu-Hsin Chen, Vivienne Sze:
A 2014 Mbin/s deeply pipelined CABAC decoder for HEVC. ICIP 2014: 2110-2114 - [c14]Amr Suleiman, Vivienne Sze:
Energy-efficient HOG-based object detection at 1080HD 60 fps with multi-scale support. SiPS 2014: 256-261 - [p2]Vivienne Sze, Detlev Marpe:
Entropy Coding in HEVC. High Efficiency Video Coding 2014: 209-274 - [p1]Mehul Tikekar, Chao-Tsung Huang, Chiraag Juvekar, Vivienne Sze, Anantha P. Chandrakasan:
Decoder Hardware Architecture for HEVC. High Efficiency Video Coding 2014: 303-341 - [e1]Vivienne Sze, Madhukar Budagavi, Gary J. Sullivan
High Efficiency Video Coding (HEVC), Algorithms and Architectures. Integrated Circuits and Systems, Springer 2014, ISBN 978-3-319-06894-7 [contents] - 2013
- [j9]Mahmut E. Sinangil, Vivienne Sze, Minhua Zhou, Anantha P. Chandrakasan:
Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard. IEEE J. Sel. Top. Signal Process. 7(6): 1017-1028 (2013) - [j8]Madhukar Budagavi, Arild Fuldseth, Gisle Bjøntegaard, Vivienne Sze, Mangesh Sadafale:
Core Transform Design in the High Efficiency Video Coding (HEVC) Standard. IEEE J. Sel. Top. Signal Process. 7(6): 1029-1041 (2013) - [c13]Chao-Tsung Huang, Mehul Tikekar, Chiraag Juvekar, Vivienne Sze, Anantha P. Chandrakasan:
A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applications. ISSCC 2013: 162-163 - [c12]Vivienne Sze, Madhukar Budagavi:
A comparison of CABAC throughput for HEVC/H.265 VS. AVC/H.264. SiPS 2013: 165-170 - 2012
- [j7]Vivienne Sze, Anantha P. Chandrakasan:
A Highly Parallel and Scalable CABAC Decoder for Next Generation Video Coding. IEEE J. Solid State Circuits 47(1): 8-22 (2012) - [j6]Vivienne Sze, Madhukar Budagavi:
High Throughput CABAC Entropy Coding in HEVC. IEEE Trans. Circuits Syst. Video Technol. 22(12): 1778-1791 (2012) - [j5]Vivienne Sze, Anantha P. Chandrakasan:
Joint Algorithm-Architecture Optimization of CABAC. J. Signal Process. Syst. 69(3): 239-252 (2012) - [c11]Madhukar Budagavi, Vivienne Sze:
Unified forward+inverse transform architecture for HEVC. ICIP 2012: 209-212 - [c10]Mahmut E. Sinangil, Anantha P. Chandrakasan, Vivienne Sze, Minhua Zhou:
Hardware-aware motion estimation search algorithm development for high-efficiency video coding (HEVC) standard. ICIP 2012: 1529-1532 - [c9]Mahmut E. Sinangil, Anantha P. Chandrakasan, Vivienne Sze, Minhua Zhou:
Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine. ICIP 2012: 1533-1536 - [c8]Vivienne Sze, Madhukar Budagavi:
Parallelization of CABAC transform coefficient coding for HEVC. PCS 2012: 509-512 - 2011
- [c7]Vivienne Sze, Anantha P. Chandrakasan:
Joint algorithm-architecture optimization of CABAC to increase speed and reduce area cost. ICASSP 2011: 1577-1580 - [c6]Madhukar Budagavi, Vivienne Sze, Minhua Zhou:
HEVC ALF decode complexity analysis and reduction. ICIP 2011: 733-736 - [c5]Vivienne Sze, Anantha P. Chandrakasan:
A highly parallel and scalable CABAC decoder for next generation video coding. ISSCC 2011: 126-128 - 2010
- [b1]Vivienne Sze:
Parallel algorithms and architectures for low power video decoding. Massachusetts Institute of Technology, Cambridge, MA, USA, 2010 - [j4]Anantha P. Chandrakasan, Denis C. Daly, Daniel F. Finchelstein, Joyce Kwong, Yogesh K. Ramadass, Mahmut E. Sinangil, Vivienne Sze, Naveen Verma:
Technologies for Ultradynamic Voltage Scaling. Proc. IEEE 98(2): 191-214 (2010)
2000 – 2009
- 2009
- [j3]Vivienne Sze, Daniel F. Finchelstein, Mahmut E. Sinangil, Anantha P. Chandrakasan:
A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder. IEEE J. Solid State Circuits 44(11): 2943-2956 (2009) - [j2]Anantha P. Chandrakasan, Fred S. Lee, David D. Wentzloff, Vivienne Sze, Brian P. Ginsburg
Low-Power Impulse UWB Architectures and Circuits. Proc. IEEE 97(2): 332-352 (2009) - [j1]Daniel F. Finchelstein, Vivienne Sze, Anantha P. Chandrakasan:
Multicore Processing and Efficient On-Chip Caching for H.264 and Future Video Decoders. IEEE Trans. Circuits Syst. Video Technol. 19(11): 1704-1713 (2009) - [c4]Vivienne Sze, Anantha P. Chandrakasan:
A high throughput CABAC algorithm using syntax element partitioning. ICIP 2009: 773-776 - 2008
- [c3]Vivienne Sze, Anantha P. Chandrakasan, Madhukar Budagavi, Minhua Zhou:
Parallel CABAC for low power video coding. ICIP 2008: 2096-2099 - 2007
- [c2]Vivienne Sze, Anantha P. Chandrakasan:
A 0.4-V UWB baseband processor. ISLPED 2007: 262-267 - 2006
- [c1]Vivienne Sze, Raúl Blázquez, Manish Bhardwaj, Anantha P. Chandrakasan:
An Energy Efficient Sub-Threshold Baseband Processor Architecture for Pulsed Ultra-Wideband Communications. ICASSP (3) 2006: 908-911
Coauthor Index
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last updated on 2024-11-08 20:34 CET by the dblp team
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