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7th NorCAS 2021: Oslo, Norway
- Jari Nurmi
, Dag T. Wisland, Snorre Aunet, Kristian Kjelgaard:
IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, Norway, October 26-27, 2021. IEEE 2021, ISBN 978-1-6654-0712-0 - Christian Westmark Sønnichsen
A Gate Voltage Sensing Ripple Reduction Control Technique for Switched-Capacitor DC-DC Converters. 1-7 - Luis Henrique Rodovalho
CMOS inverter linearization technique with active source degeneration. 1-6 - Chuanjun Zhang, Shivangi Katiyar, Mitch Diamond, Olivier Franza:
Approximate Computation on Commodity Computers through Bit-Serial Processing. 1-7 - Li Lu
Machine Learning Approach for Accelerating Simulation-based Fault Injection. 1-6 - Milad Zamani, Yasser Rezaeiyan, Omid Shoaei, Farshad Moradi:
A 7.2µW Magnitude/Phase Bio-impedance Measurement Front-End with PWM Output in 0.18µm CMOS. 1-5 - Mehdi Safarpour, Tommy Z. Deng, John Massingham, Lei Xun, Mohammad Sabokrou, Olli Silvén:
Low-Voltage Energy Efficient Neural Inference by Leveraging Fault Detection Techniques. 1-5 - Shadi M. Harb, William R. Eisenstadt
Signal Integrity in High Speed 3D IC Design- A Case Study. 1-5 - Sauli Haukka, Jere Rusanen, Alok Sethi, Aarno Pärssinen
Broadband Analog Predistortion Circuits Utilizing Derivative Superposition. 1-5 - Oscar Morales Chacon
A digital switching scheme to reduce DAC glitches using code-dependent randomization. 1-5 - Carmine Paolino, Fabio Pareschi, Mauro Mangia, Riccardo Rovatti, Gianluca Setti:
An architecture for ultra-low-voltage ultra-low-power compressed sensing-based acquisition systems. 1-7 - Panu Sjövall
High-Level Synthesis Implementation of an Accurate HEVC Interpolation Filter on an FPGA. 1-7 - Rikard Gannedahl
An LO Frequency Tripler with Phase Shifter and Detector in 28nm FD-SOI CMOS for 28-GHz Transceivers. 1-7 - Tobias Stuckenberg, Malte Rücker, Niklas Rother
Powerline Communication System-on-Chip in 180 nm Harsh Environment SOI Technology. 1-5 - Clemens Pircher, Alexander Baranyai, Christoph Lehr, Martin Schoeberl
Accelerator Interface for Patmos. 1-7 - Dimitrios Stathis
Clock Tree Generation by Abutment in Synchoros VLSI Design. 1-7 - Jari Nurmi
Intelligent Cognitive Radio Architecture Applying Machine Learning and Reconfigurability. 1-6 - Luis Henrique Rodovalho
A Two-Stage Single-Ended OTA with Improved Composite Transistors. 1-7 - Markus Mogensen Henriksen
Analysis and Design of Start-up Circuits for a 48 V-12 V Switched-Capacitor Converter in a 180 nm SOI Process. 1-7 - Topi Leppänen
Unified OpenCL Integration Methodology for FPGA Designs. 1-7 - Midia Reshadi, David Gregg:
LOCAL: Low-Complex Mapping Algorithm for Spatial DNN Accelerators. 1-7 - Ping Lu:
A 25.6-27.5GHz Phase-Locked Loop for SerDes Transceiver Clocking in 5nm FinFET. 1-4 - Meenali Janveja, Mayank Tantuway, Ketan Chaudhari, Gaurav Trivedi:
Design of Low Power VLSI Architecture for Classification of Arrhythmic Beats Using DNN for Wearable Device Applications. 1-6 - Mohammad Reza Heidari Iman, Jaan Raik, Maksim Jenihhin, Gert Jervan, Tara Ghasempouri
A Methodology for Automated Mining of Compact and Accurate Assertion Sets. 1-7 - Marcel Jotschke, Gokulkumar Palanisamy, Wilmar Carvajal Ossa, Harsha Prabakaran, Jeongwook Koh, Matthias Kuhl
Low Power CMOS Thyristor-Based Relaxation Oscillator with Efficient Current Compensation. 1-5 - Cristina Missel Adornes
Bridging the gap between design and simulation of low voltage CMOS circuits. 1-5 - Daniela Sanchez Lopera
RTL Delay Prediction Using Neural Networks. 1-7 - Andrew Dobis
ChiselVerify: An Open-Source Hardware Verification Library for Chisel and Scala. 1-7 - Zain Taufique
Approximate Feature Extraction for Low Power Epileptic Seizure Prediction in Wearable Devices. 1-7 - Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet:
Subthreshold Power PC and Nand Race-Free Flip-Flops in Frequency Divider Applications. 1-6 - Zihao Jiao, Xiaofei Wang, Hongrui Luo, Jie Zhang, Ruizhi Zhang, Hong Zhang:
Linearity Boosting Technique with Adaptive Sampling Switch Assisted by Signal Prediction for Multi-Channel ADCs in Standard CMOS Process. 1-5 - Harshitha Basavaraju, David Borggreve
A 0.8-V, 2.88-GHz Double-Tail Latched Comparator in 22-nm FDSOI CMOS Technology. 1-6 - Giovanni Mezzina, Daniela De Venuto:
Low-Complexity Unidimensional CNN based Brain Speller for Embedded Platforms. 1-6
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