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Yohei Nakata
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2020 – today
- 2024
- [c19]Rongyu Zhang, Yulin Luo, Jiaming Liu, Huanrui Yang, Zhen Dong, Denis A. Gudovskiy, Tomoyuki Okuno, Yohei Nakata, Kurt Keutzer, Yuan Du, Shanghang Zhang:
Efficient Deweahter Mixture-of-Experts with Uncertainty-Aware Feature-Wise Linear Modulation. AAAI 2024: 16812-16820 - [c18]Anthony Chen, Huanrui Yang, Yulu Gan, Denis A. Gudovskiy, Zhen Dong, Haofan Wang, Tomoyuki Okuno, Yohei Nakata, Kurt Keutzer, Shanghang Zhang:
Split-Ensemble: Efficient OOD-aware Ensemble via Task and Model Splitting. ICML 2024 - [c17]Rongyu Zhang, Zefan Cai, Huanrui Yang, Zidong Liu, Denis A. Gudovskiy, Tomoyuki Okuno, Yohei Nakata, Kurt Keutzer, Baobao Chang, Yuan Du, Li Du, Shanghang Zhang:
VeCAF: Vision-language Collaborative Active Finetuning with Training Objective Awareness. ACM Multimedia 2024: 5451-5459 - [c16]Jumpei Goto, Yohei Nakata, Kiyofumi Abe, Yasunori Ishii, Takayoshi Yamashita:
Learning Intra-class Multimodal Distributions with Orthonormal Matrices. WACV 2024: 1859-1868 - [i9]Rongyu Zhang, Zefan Cai, Huanrui Yang, Zidong Liu, Denis A. Gudovskiy, Tomoyuki Okuno, Yohei Nakata, Kurt Keutzer, Baobao Chang, Yuan Du, Li Du, Shanghang Zhang:
VeCAF: VLM-empowered Collaborative Active Finetuning with Training Objective Awareness. CoRR abs/2401.07853 (2024) - [i8]Denis A. Gudovskiy, Tomoyuki Okuno, Yohei Nakata:
ContextFlow++: Generalist-Specialist Flow-based Generative Models with Mixed-Variable Context Encoding. CoRR abs/2406.00578 (2024) - [i7]Huanrui Yang, Yafeng Huang, Zhen Dong, Denis A. Gudovskiy, Tomoyuki Okuno, Yohei Nakata, Yuan Du, Kurt Keutzer, Shanghang Zhang:
Fisher-aware Quantization for DETR Detectors with Critical-category Objectives. CoRR abs/2407.03442 (2024) - [i6]Yuan Zhang, Chun-Kai Fan, Junpeng Ma, Wenzhao Zheng, Tao Huang, Kuan Cheng, Denis A. Gudovskiy, Tomoyuki Okuno, Yohei Nakata, Kurt Keutzer, Shanghang Zhang:
SparseVLM: Visual Token Sparsification for Efficient Vision-Language Model Inference. CoRR abs/2410.04417 (2024) - 2023
- [c15]Denis A. Gudovskiy, Tomoyuki Okuno, Yohei Nakata:
Concurrent Misclassification and Out-of-Distribution Detection for Semantic Segmentation via Energy-Based Normalizing Flow. UAI 2023: 745-755 - [i5]Denis A. Gudovskiy, Tomoyuki Okuno, Yohei Nakata:
Concurrent Misclassification and Out-of-Distribution Detection for Semantic Segmentation via Energy-Based Normalizing Flow. CoRR abs/2305.09610 (2023) - [i4]Anthony Chen, Huanrui Yang, Yulu Gan, Denis A. Gudovskiy, Zhen Dong, Haofan Wang, Tomoyuki Okuno, Yohei Nakata, Shanghang Zhang, Kurt Keutzer:
Split-Ensemble: Efficient OOD-aware Ensemble via Task and Model Splitting. CoRR abs/2312.09148 (2023) - [i3]Rongyu Zhang, Yulin Luo, Jiaming Liu, Huanrui Yang, Zhen Dong, Denis A. Gudovskiy, Tomoyuki Okuno, Yohei Nakata, Kurt Keutzer, Yuan Du, Shanghang Zhang:
Efficient Deweather Mixture-of-Experts with Uncertainty-aware Feature-wise Linear Modulation. CoRR abs/2312.16610 (2023) - 2022
- [c14]Jinze Yu, Jiaming Liu, Xiaobao Wei, Haoyi Zhou, Yohei Nakata, Denis A. Gudovskiy, Tomoyuki Okuno, Jianxin Li, Kurt Keutzer, Shanghang Zhang:
MTTrans: Cross-domain Object Detection with Mean Teacher Transformer. ECCV (9) 2022: 629-645 - [i2]Jinze Yu, Jiaming Liu, Xiaobao Wei, Haoyi Zhou, Yohei Nakata, Denis A. Gudovskiy, Tomoyuki Okuno, Jianxin Li, Kurt Keutzer, Shanghang Zhang:
Cross-Domain Object Detection with Mean-Teacher Transformer. CoRR abs/2205.01643 (2022) - 2021
- [c13]Tomoyuki Okuno, Yohei Nakata, Yasunori Ishii, Sotaro Tsukizawa:
Lossless AI: Toward Guaranteeing Consistency between Inferences Before and After Quantization via Knowledge Distillation. MVA 2021: 1-5 - 2020
- [i1]Stefano Alletto, Shenyang Huang, Vincent François-Lavet, Yohei Nakata, Guillaume Rabusseau:
RandomNet: Towards Fully Automatic Neural Architecture Design for Multimodal Learning. CoRR abs/2003.01181 (2020)
2010 – 2019
- 2015
- [j8]Go Matsukawa, Yohei Nakata, Yasuo Sugure, Shigeru Oho, Yuta Kimi, Masafumi Shimozawa, Shuhei Yoshida, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme. IEICE Trans. Electron. 98-C(4): 333-339 (2015) - 2014
- [j7]Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation. IEICE Trans. Electron. 97-C(4): 332-341 (2014) - [c12]Go Matsukawa, Yohei Nakata, Yuta Kimi, Yasuo Sugure, Masafumi Shimozawa, Shigeru Oho, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM. ARCS Workshops 2014: 1-5 - [c11]Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement. ISQED 2014: 16-23 - 2013
- [j6]Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM. IEICE Trans. Electron. 96-C(4): 528-537 (2013) - [c10]Jinwook Jung, Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi:
Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags. ISQED 2013: 216-222 - 2012
- [j5]Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy. IEICE Electron. Express 9(6): 470-476 (2012) - [j4]Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing. IEICE Trans. Electron. 95-C(4): 523-533 (2012) - [j3]Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme. Inf. Media Technol. 7(2): 544-555 (2012) - [j2]Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme. IPSJ Trans. Syst. LSI Des. Methodol. 5: 32-43 (2012) - [c9]Koji Kugata, Shinpei Soda, Yohei Nakata, Shunsuke Okumura, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
Processor Coupling Architecture for Aggressive Voltage Scaling on Multicores. ARCS Workshops 2012: 375-384 - [c8]Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, Shusuke Yoshimoto, Yohei Nakata, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Bit error rate estimation in SRAM considering temperature fluctuation. ISQED 2012: 516-519 - 2011
- [j1]Shunsuke Okumura, Yuki Kagiyama, Yohei Nakata, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2693-2700 (2011) - [c7]Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy. CICC 2011: 1-4 - [c6]Yohei Nakata, Yukihiro Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers. DSD 2011: 801-804 - [c5]Yohei Nakata, Yasuhiro Ito, Yasuo Sugure, Shigeru Oho, Yusuke Takeuchi, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Model-based fault injection for failure effect analysis - Evaluation of dependable SRAM for vehicle control units. DSN Workshops 2011: 91-96 - [c4]Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V. ICECS 2011: 524-527 - [c3]Masahiro Yoshikawa, Shunsuke Okumura, Yohei Nakata, Yuki Kagiyama, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control. ISQED 2011: 322-325 - 2010
- [c2]Shunsuke Okumura, Shusuke Yoshimoto, Kosuke Yamaguchi, Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto:
7T SRAM enabling low-energy simultaneous block copy. CICC 2010: 1-4 - [c1]Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM. ISLPED 2010: 219-224
Coauthor Index
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