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Hiroshi Miyashita
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2020 – today
- 2023
- [c12]Noriko H. Arai, Ryuji Masukawa, Hiroshi Miyashita:
Designing Researchmap: A Revolutionary Scholar Support Platform Achieved Through Human-AI Collaboration. ICKII 2023: 367-371 - 2021
- [j5]Hiroshi Miyashita:
Human-centric data protection laws and policies: A lesson from Japan. Comput. Law Secur. Rev. 40: 105487 (2021) - [c11]Ken Namura, Johannes Maximilian Kühn, Tohru Adachi, H. Imachi, H. Kaneko, T. Kato, Go Watanabe, Naoto Tanaka, S. Kashihara, Hiroshi Miyashita, Y. Tomonaga, Ryosuke Okuta, Takuya Akiba, Brian Vogel, S. Kitajo, F. Osawa, K. Takahashi, Y. Takatsukasa, K. Mizumaru, T. Yamauchi, J. Ono, A. Takahashi, Tanvir Ahmed, Y. Doi, K. Hiraki, J. Makino:
MN-Core - A Highly Efficient and Scalable Approach to Deep Learning. VLSI Circuits 2021: 1-2
2010 – 2019
- 2017
- [c10]Mio Kobayashi, Ai Ishii, Chikara Hoshino, Hiroshi Miyashita, Takuya Matsuzaki:
Automated Historical Fact-Checking by Passage Retrieval, Word Statistics, and Virtual Question-Answering. IJCNLP(1) 2017: 967-975 - 2016
- [c9]Mio Kobayashi, Hiroshi Miyashita, Ai Ishii, Chikara Hoshino:
NUL System at QA Lab-2 Task. NTCIR 2016 - 2014
- [c8]Ai Ishii, Hiroshi Miyashita, Mio Kobayashi, Chikara Hoshino:
NUL System at NTCIR RITE-VAL Tasks. NTCIR 2014 - [c7]Hiroshi Miyashita, Ai Ishii, Mio Kobayashi, Chikara Hoshino:
NUL System at QALab Tasks. NTCIR 2014 - 2013
- [c6]Hiroshi Miyashita, Shin-ichiro Katsuda:
Basis of monitoring central blood pressure and hemodynamic parameters by peripheral arterial pulse waveform analyses. EMBC 2013: 221-224
2000 – 2009
- 2007
- [c5]Jing Li, Hiroshi Miyashita:
Efficient Thermal Via Planning for Placement of 3D Integrated Circuits. ISCAS 2007: 145-148 - 2006
- [j4]Jing Li, Hiroshi Miyashita:
Thermal-Aware Placement Based on FM Partition Scheme and Force-Directed Heuristic. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 989-995 (2006) - [c4]Jing Li, Hiroshi Miyashita:
Post-placement Thermal Via Planning for 3D Integrated Circuit. APCCAS 2006: 808-811 - 2005
- [j3]Jing Li, Juebang Yu, Hiroshi Miyashita:
An Incremental Placement Algorithm for Building Block Layout Design Based on the O-Tree Representation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3398-3404 (2005) - [j2]Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi:
Equidistance routing in high-speed VLSI layout design. Integr. 38(3): 439-449 (2005) - 2004
- [c3]Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi:
Equidistance routing in high-speed VLSI layout design. ACM Great Lakes Symposium on VLSI 2004: 220-223 - 2002
- [c2]Hiroshi Miyashita, Yoji Kajitani:
On the equivalence of the sequence pair for rectangle packing to the dimension of partial orders [floorplanning]. APCCAS (2) 2002: 367-370
1990 – 1999
- 1995
- [c1]Hiroshi Miyashita:
Extending pitchmaking algorithms to layouts with multiple grid constraints. ASP-DAC 1995
1980 – 1989
- 1986
- [j1]Hiroshi Miyashita, Tohru Adachi, Kazuhiro Ueda:
An automatic cell pattern generation system for CMOS transistor-pair array LSI. Integr. 4(2): 115-133 (1986)
Coauthor Index
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