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Yukiya Miura
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2020 – today
- 2024
- [c44]Yuki Hanawa, Tomohiro Harada, Yukiya Miura:
Analysis of the Impact of Prediction Accuracy on Search Performance in Surrogate-assisted Evolutionary Algorithms. CEC 2024: 1-8 - [c43]Akito Takenaka, Tomohiro Harada, Yukiya Miura, Kiyohiko Hattori, Johei Matuoka:
Cooperative Autonomous Driving Control among Vehicles of Different Sizes Using Deep Reinforcement Learning. IJCNN 2024: 1-8 - 2023
- [c42]Hitomi Kano
, Tomohiro Harada
Hybrid Rocket Engine Design Using Pairwise Ranking Surrogate-assisted Differential Evolution. GECCO Companion 2023: 1956-1962 - [c41]Reo Nakaya, Tomohiro Harada, Yukiya Miura, Kiyohiko Hattori, Johei Matsuoka:
Emergence of Cooperative Automated Driving Control at Roundabouts Using Deep Reinforcement Learning. SICE 2023: 97-102 - 2022
- [c40]Takuya Hakoishi, Tomohiro Harada, Yukiya Miura:
Improving Data Sampling Efficiency of Sensitivity Analysis Based on Bilevel Multi-objective Evolutionary Algorithm. SCIS/ISIS 2022: 1-6 - [c39]Hitomi Kano, Tomohiro Harada, Yukiya Miura:
Differential Evolution Using Surrogate Model Based on Pairwise Ranking Estimation for Constrained Optimization Problems. SCIS/ISIS 2022: 1-6 - 2021
- [c38]Yukiya Miura, Shingo Tsutsumi:
A Method for Measuring Process Variations in the FPGA Chip Considering the Effect of Wire Delay. IOLTS 2021: 1-6 - 2020
- [c37]Yukiya Miura, Yuya Kinoshita:
Soft Error Tolerance of Power-Supply-Noise Hardened Latches. IOLTS 2020: 1-6 - [c36]Yousuke Miyake
On-Chip Delay Measurement for Degradation Detection And Its Evaluation under Accelerated Life Test. IOLTS 2020: 1-6 - [c35]Takeshi Iwasaki, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yousuke Miyake
Innovative Test Practices in Asia. VTS 2020: 1
2010 – 2019
- 2019
- [c34]Yukiya Miura, Miyuki Inoue, Yuya Kinoshita:
Development of FF Circuits for Measures Against Power Supply Noise. IOLTS 2019: 48-51 - 2017
- [c33]Yukiya Miura, Takuya Yamamoto:
Simulation-based analysis of FF behavior in presence of power supply noise. IOLTS 2017: 151-156 - 2016
- [j12]Yousuke Miyake
Temperature and Voltage Measurement for Field Test Using an Aging-Tolerant Monitor. IEEE Trans. Very Large Scale Integr. Syst. 24(11): 3282-3295 (2016) - 2015
- [c32]Yukiya Miura, Tatsunori Ikeda:
LSI aging estimation using ring oscillators. ETS 2015: 1-2 - 2014
- [c31]Yousuke Miyake
Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test. ATS 2014: 156-161 - [c30]Seiji Kajihara, Yousuke Miyake
An On-Chip Digital Environment Monitor for Field Test. ATS 2014: 254-257 - [c29]Yukiya Miura, Yoshihiro Ohkawa:
A noise-tolerant master-slave flip-flop. IOLTS 2014: 55-61 - 2012
- [c28]Yoshihiro Ohkawa, Yukiya Miura:
Dual Edge Triggered Flip-Flops for Noise Blocking and Application to Signal Delay Detection. Asian Test Symposium 2012: 119-124 - [c27]Yukiya Miura, Yasuo Sato, Yousuke Miyake
On-chip temperature and voltage measurement for field testing. ETS 2012: 1 - [c26]Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura:
DART: Dependable VLSI test architecture and its implementation. ITC 2012: 1-10 - 2011
- [c25]Yukiya Miura:
Dual Edge Triggered Flip-Flops for Noise Aware Design. ETS 2011: 217 - [c24]Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi, Yukiya Miura:
A supply current testable register string DAC of decoder type. ISCIT 2011: 58-63 - 2010
- [c23]Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura:
On estimation of NBTI-Induced delay degradation. ETS 2010: 107-111
2000 – 2009
- 2008
- [j11]Yukiya Miura, Jiro Kato:
Adaptive Fault Diagnosis of Analog Circuits by Operation-Region Model and X - Y Zoning Method. J. Electron. Test. 24(1-3): 223-233 (2008) - [j10]Yukiya Miura:
Ramp Voltage Testing for Detecting Interconnect Open Faults. IEICE Trans. Inf. Syst. 91-D(3): 700-705 (2008) - [c22]Yukiya Miura, Jiro Kato:
Diagnosis of Analog Circuits by Using Multiple Transistors and Data Sampling. DFT 2008: 491-499 - 2007
- [c21]Masaki Hashizume, Yutaka Hata, Tomomi Nishida, Hiroyuki Yotsuyanagi, Yukiya Miura:
Current Testable Design of Resistor String DACs. ATS 2007: 399-403 - [c20]Yukiya Miura:
Dependable clock distribution for crosstalk aware design. ITC 2007: 1-9 - 2006
- [j9]Yukiya Miura:
Proposal of Fault Diagnosis of Analog Circuits by Combining Operation-Region Model and X-Y Zoning Method: Case Study. J. Electron. Test. 22(4-6): 411-423 (2006) - [c19]Yukiya Miura:
Detection of Interconnect Open Faults with Unknown Values by Ramp Voltage Application. ATS 2006: 55-62 - [c18]Masato Nakanishi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Yukiya Miura:
A BIC Sensor Capable of Adjusting IDDQ Limit in Tests. ATS 2006: 69-74 - [c17]Masaki Hashizume, Tomomi Nishida, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura:
Current Testable Design of Resistor String DACs. DELTA 2006: 197-200 - [c16]Yukiya Miura, Jiro Kato:
Fault Diagnosis of Analog Circuits Based on Adaptive Test and Output Characteristics. DFT 2006: 410-418 - 2005
- [c15]Yukiya Miura:
Characteristics of Fault Diagnosis for Analog Circuits Based on Preset Test. DFT 2005: 573-581 - 2004
- [j8]Yukiya Miura:
Analysis and Testing of Bridging Faults in CMOS Synchronous Sequential Circuits. IEICE Trans. Inf. Syst. 87-D(3): 564-570 (2004) - [c14]Yukiya Miura:
Fault Diagnosis of Analog Circuits by Operation-Region Model and X-Y Zoning Method. DFT 2004: 230-238 - 2003
- [c13]Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita:
A BIST Circuit for IDDQ Tests. Asian Test Symposium 2003: 390-395 - [c12]Yukiya Miura, Daisuke Kato:
Analysis and Testing of Analog and Mixed-Signal Circuits by an Operation-Region Model: A Case Study of Application and Implementation. DFT 2003: 279-286 - 2002
- [j7]Yukiya Miura, Shuichi Seno:
Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits. J. Electron. Test. 18(2): 109-120 (2002) - 2001
- [c11]Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita:
IDDQ Sensing Technique for High Speed IDDQ Testing. Asian Test Symposium 2001: 111-116 - [c10]Yukiya Miura, Shuichi Seno:
Internal feedback bridging faults in combinational CMOS circuits: analysis and testing. ETW 2001: 9-16 - [c9]Yukiya Miura:
Proposal of an Operation-Region Model for Analyzing Analog and Mixed-Signal Circuits. LATW 2001: 118-125 - 2000
- [c8]Arabi Keshk, Yukiya Miura, Kozo Kinoshita:
Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits. Asian Test Symposium 2000: 120-124
1990 – 1999
- 1999
- [j6]Yukiya Miura, Hiroshi Yamazaki:
A Low-Loss Built-In Current Sensor. J. Electron. Test. 14(1-2): 39-48 (1999) - [c7]Arabi Keshk, Kozo Kinoshita, Yukiya Miura:
Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits. Asian Test Symposium 1999: 121-126 - [c6]Arabi Keshk, Kozo Kinoshita, Yukiya Miura:
IDDQ Current Dependency on Test Vectors and Bridging Resistance. Asian Test Symposium 1999: 158-163 - 1998
- [c5]Masaki Hashizume, Yukiya Miura, Masahiro Ichimiya, Takeomi Tamesada, Kozo Kinoshita:
A High-Speed IDDQ Sensor for Low-Voltage ICs. Asian Test Symposium 1998: 327- - 1997
- [c4]Yukiya Miura:
An IDDQ Sensor Circuit for Low-Voltage ICs. ITC 1997: 938-947 - 1996
- [j5]Yukiya Miura:
Real-Time Current Testing for A/D Converters. IEEE Des. Test Comput. 13(2): 34-41 (1996) - 1995
- [j4]Yukiya Miura, Sachio Naito:
A Method of Current Testing for CMOS Digital and Mixed-Signal LSIs. IEICE Trans. Inf. Syst. 78-D(7): 845-852 (1995) - [c3]Yukiya Miura:
A Comparative Analysis of Input Stimuli for Testing Mixed-Signal LSIs Based on Curent Testing. ITC 1995: 71-77 - 1994
- [c2]Yukiya Miura, Sachio Naito, Kozo Kinoshita:
A Case Study of Mixed-Signal Integrated Circuit Testing: An Application of Current Testing Using the Upper Limit and the Lower Limit. ISCAS 1994: 77-80 - 1993
- [j3]Yukiya Miura, Yasushi Wada, Kozo Kinoshita:
Design of testing circuit and test generation for built-in current testing. Syst. Comput. Jpn. 24(5): 73-82 (1993) - 1992
- [c1]Yukiya Miura, Kozo Kinoshita:
Circuit Design for Built-in Current Testing. ITC 1992: 873-881
1980 – 1989
- 1988
- [j2]Yukiya Miura, Hideo Tamamoto, Yuichi Narita:
Built - in concurrent testing for semiconductor random access memories by concurrently testing cells on a word-line. Syst. Comput. Jpn. 19(6): 50-62 (1988) - 1987
- [j1]Yukiya Miura, Hideo Tamamoto, Yuichi Narita:
A built-in test for functional testing in semiconductor random access memory. Syst. Comput. Jpn. 18(9): 64-73 (1987)
Coauthor Index
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