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René Cumplido
René Cumplido-Parra
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- affiliation: National Institute of Astrophysics, Optics and Electronics, Puebla, Mexico
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2020 – today
- 2024
- [j52]Martín Letras
, Alicia Morales-Reyes
A novel partition strategy for efficient implementation of 3D Cellular Genetic Algorithms. Microprocess. Microsystems 104: 104986 (2024) - 2023
- [j51]Alejandro Peñuelas-Angulo
An adaptive method for prevention of overflow in reversible data hiding schemes. Expert Syst. Appl. 230: 120610 (2023) - [j50]G. Melendez-Melendez
An adaptive pixel value ordering based reversible data hiding scheme for images. Expert Syst. Appl. 232: 120809 (2023) - [j49]A. Hernández-Joaquín, G. Melendez-Melendez, René Cumplido
A secure DWT-based dual watermarking scheme for image authentication and copyright protection. Multim. Tools Appl. 82(27): 42739-42761 (2023) - 2022
- [j48]Lázaro Bustio-Martínez
FPGA/GPU-based Acceleration for Frequent Itemsets Mining: A Comprehensive Review. ACM Comput. Surv. 54(9): 179:1-179:35 (2022) - [j47]Lázaro Bustio-Martínez
A lightweight data representation for phishing URLs detection in IoT environments. Inf. Sci. 603: 42-59 (2022) - [c48]G. Melendez-Melendez
Reversible Image Authentication Scheme with Tampering Reconstruction Based on Very Deep Super Resolution Network. MICAI (1) 2022: 308-326 - 2021
- [j46]Jorge Echavarria, Alicia Morales-Reyes, René Cumplido, Miguel A. Salido, Claudia Feregrino Uribe:
IP-cores watermarking scheme at behavioral level using genetic algorithms. Eng. Appl. Artif. Intell. 104: 104386 (2021) - [j45]Miguel Morales-Sandoval
A Compact FPGA-Based Accelerator for Curve-Based Cryptography in Wireless Sensor Networks. J. Sensors 2021: 8860413:1-8860413:13 (2021) - 2020
- [j44]Martín Letras
On the design of hardware architectures for parallel frequent itemsets mining. Expert Syst. Appl. 157: 113440 (2020)
2010 – 2019
- 2019
- [j43]Ernesto Aparicio-Díaz, René Cumplido, Maikel L. Pérez Gort
Temporal Copy-Move Forgery Detection and Localization Using Block Correlation Matrix. J. Intell. Fuzzy Syst. 36(5): 5023-5035 (2019) - [j42]Lázaro Bustio-Martínez
Using hashing and lexicographic order for Frequent Itemsets Mining on data streams. J. Parallel Distributed Comput. 125: 58-71 (2019) - [j41]René Cumplido, Maya B. Gokhale, Claudia Feregrino, Michael Hübner:
Guest Editorial: Special Issue on Reconfigurable Computing and FPGA Technology. J. Parallel Distributed Comput. 133: 359-361 (2019) - [j40]Lázaro Bustio-Martínez
A novel multi-core algorithm for frequent itemsets mining in data streams. Pattern Recognit. Lett. 125: 241-248 (2019) - [c47]Ernesto Aparicio-Díaz, René Cumplido, Lázaro Bustio-Martínez
Detection And Localization Of Splicing Attacks On Videos Using Block Correlation. PACRIM 2019: 1-6 - [e8]David Andrews, René Cumplido, Claudia Feregrino, Marco Platzner:
2019 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2019, Cancun, Mexico, December 9-11, 2019. IEEE 2019, ISBN 978-1-7281-1957-1 [contents] - 2018
- [j39]Lázaro Bustio-Martínez
On the design of hardware-software architectures for frequent itemsets mining on data streams. J. Intell. Inf. Syst. 50(3): 415-440 (2018) - [e7]David Andrews, René Cumplido, Claudia Feregrino, Dirk Stroobandt:
2018 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, December 3-5, 2018. IEEE 2018, ISBN 978-1-7281-1968-7 [contents] - [i2]Eduardo Cuevas-Farfan, Miguel Morales-Sandoval, René Cumplido:
An FPGA-based programmable processor for bilinear pairings. IACR Cryptol. ePrint Arch. 2018: 1014 (2018) - 2017
- [j38]Roberto de Lima
Improving the construction of ORB through FPGA-based acceleration. Mach. Vis. Appl. 28(5-6): 525-537 (2017) - [c46]Lázaro Bustio-Martínez
Approximate frequent itemsets mining on data streams using hashing and lexicographie order in hardware. LASCAS 2017: 1-4 - [c45]Luis Armando Rodriguez Flores, Miguel Morales-Sandoval
A compact FPGA-based microcoded coprocessor for exponentiation in asymmetric encryption. LASCAS 2017: 1-4 - 2016
- [j37]René Cumplido, Peter Athanas, Eduardo de la Torre:
Introduction to the Special Section on FPGAs Technology and Applications. Comput. Electr. Eng. 49: 67-68 (2016) - [j36]René Cumplido, Michael Hübner, Michael J. Wirthlin:
Introduction to the special section on FPGAs Technology and Applications. Comput. Electr. Eng. 55: 88-90 (2016) - [j35]Martín Letras
A scalable and customizable processor array for implementing cellular genetic algorithms. Neurocomputing 175: 899-910 (2016) - [c44]Juan Andrés Pérez-Celis, José Martínez-Carranza
An FPGA Architecture to Accelerate the Burrows Wheeler Transform by Using a Linear Sorter. IPDPS Workshops 2016: 156-161 - [c43]Martín Letras
Hardware Architectures for Frequent Itemset Mining Based on Equivalence Classes Partitioning. IPDPS Workshops 2016: 289-294 - [e6]Peter M. Athanas, René Cumplido, Claudia Feregrino, Ron Sass:
International Conference on ReConFigurable Computing and FPGAs, ReConFig 2016, Cancun, Mexico, November 30 - Dec. 2, 2016. IEEE 2016, ISBN 978-1-5090-3707-0 [contents] - 2015
- [j34]Marisol Rodriguez-Perez, Alicia Morales-Reyes
An analysis of computational models for accelerating the subtractive pixel adjacency model computation. Comput. Electr. Eng. 43: 9-16 (2015) - [j33]Vladimir Rodríguez-Diez
A fast hardware software platform for computing irreducible testors. Expert Syst. Appl. 42(24): 9612-9619 (2015) - [j32]René Cumplido, Eduardo de la Torre, Claudia Feregrino Uribe, Michael J. Wirthlin:
Introduction to Special issue on Reconfigurable computing and FPGAs. Microprocess. Microsystems 39(7): 541-542 (2015) - [j31]Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido:
Processor arrays generation for matrix algorithms used in embedded platforms implemented on FPGAs. Microprocess. Microsystems 39(7): 576-588 (2015) - [c42]Alicia Morales-Reyes
An Empirical Analysis on Dimensionality in Cellular Genetic Algorithms. GECCO 2015: 895-902 - [c41]Lázaro Bustio
Frequent Itemsets Mining in Data Streams Using Reconfigurable Hardware. NFMCP 2015: 32-45 - [c40]Maya B. Gokhale, Michael Hübner, René Cumplido:
Message from chairs. ReConFig 2015: 1 - [c39]Roberto de Lima, José Martínez-Carranza
Accelerating the construction of BRIEF descriptors using an FPGA-based architecture. ReConFig 2015: 1-6 - [e5]Michael Hübner, Maya B. Gokhale, René Cumplido:
International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, Riviera Maya, Mexico, December 7-9, 2015. IEEE 2015, ISBN 978-1-4673-9406-2 [contents] - 2014
- [j30]Rommel García, Ignacio Algredo-Badillo
A compact FPGA-based processor for the Secure Hash Algorithm SHA-256. Comput. Electr. Eng. 40(1): 194-202 (2014) - [j29]Peter Athanas, René Cumplido, Eduardo de la Torre:
Introduction to the special issue on FPGA Technology and Applications. Comput. Electr. Eng. 40(4): 1143-1145 (2014) - [j28]Claudia Feregrino Uribe, Ernesto Aparicio-Díaz, José Juan García-Hernández, Alejandra Menendez-Ortiz, René Cumplido, Alicia Morales-Reyes
Hardware architecture for security improved Fallahpour audio watermarking scheme. IEICE Electron. Express 11(9): 20140223 (2014) - [j27]Tomás Balderas-Contreras, René Cumplido, Gustavo Rodríguez Gómez:
Synthesizing VHDL from Activity Models in UML 2. Int. J. Circuit Theory Appl. 42(5): 542-550 (2014) - [j26]Peter M. Athanas, René Cumplido, Claudia Feregrino Uribe, Eduardo de la Torre:
Introduction to Special issue on FPGA Devices and Applications. Microprocess. Microsystems 38(8): 843-844 (2014) - [j25]Lázaro Bustio-Martínez, René Cumplido-Parra, Raudel Hernández-León, Claudia Feregrino Uribe:
Hardware Acceleration of Frequent Itemsets Mining on Data Streams. Res. Comput. Sci. 71: 13-22 (2014) - [c38]José Manuel Bande Serrano, José Hernández Palancar, René Cumplido:
The Evaluation of Ordered Features for SMS Spam Filtering. CIARP 2014: 383-390 - [c37]Jorge Echavarria
FSM merging and reduction for IP cores watermarking using Genetic Algorithms. ReConFig 2014: 1-7 - [c36]Vladimir Rodriguez
A hardware architecture for filtering irreducible testors. ReConFig 2014: 1-4 - 2013
- [j24]Miguel Morales-Sandoval
Area/performance trade-off analysis of an FPGA digit-serial GF(2m)GF(2m) Montgomery multiplier based on LFSR. Comput. Electr. Eng. 39(2): 542-549 (2013) - [j23]Jose Juan Garcia-Hernandez, Ramón Parra-Michel, Claudia Feregrino Uribe, René Cumplido:
High payload data-hiding in audio signals based on a modified OFDM approach. Expert Syst. Appl. 40(8): 3055-3064 (2013) - [j22]Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido, Juan M. Campos:
On an external memory scheme for processor arrays. IEICE Electron. Express 10(14): 20130324 (2013) - [j21]René Cumplido, Peter Athanas, Jürgen Becker:
Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011). Int. J. Reconfigurable Comput. 2013: 597323:1-597323:2 (2013) - [j20]Ignacio Algredo-Badillo
FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256. Microprocess. Microsystems 37(6-7): 750-757 (2013) - [j19]José Manuel Bande Serrano, José Hernández Palancar, René Cumplido:
Multi-character cost-effective and high throughput architecture for content scanning. Microprocess. Microsystems 37(8-D): 1200-1207 (2013) - [j18]Diana Goehringer, René Cumplido:
Introduction to the special section on 19th reconfigurable architectures workshop (RAW 2012). ACM Trans. Reconfigurable Technol. Syst. 6(2): 6:1 (2013) - [c35]José Manuel Bande Serrano, José Hernández Palancar, René Cumplido:
High Throughput Signature Based Platform for Network Intrusion Detection. CIARP (2) 2013: 544-551 - [c34]Jürgen Becker, Ramachandran Vaidyanathan, Peter Athanas, Marco D. Santambrogio
RAW Introduction. IPDPS Workshops 2013: 103-105 - [c33]Francisco Aguirre-Ramos
Video Error Concealment Based on Data Hiding for the Emerging Video Technologies. PSIVT 2013: 454-467 - [c32]Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido, Juan M. Campos:
Processor arrays generation for matrix algorithms used in embedded platforms. ReConFig 2013: 1-6 - [c31]Juan M. Campos, René Cumplido, Claudia Feregrino Uribe, Roberto Perez-Andrade:
A parallelization methodology for reconfigurable systems applied to edge detection. ReCoSoC 2013: 1-7 - [c30]Eduardo Cuevas-Farfan, Miguel Morales-Sandoval
A programmable FPGA-based cryptoprocessor for bilinear pairings over F2m. ReCoSoC 2013: 1-8 - 2012
- [j17]Pedro Aaron Hernandez-Avalos, Claudia Feregrino Uribe, René Cumplido:
Watermarking using similarities based on fractal codification. Digit. Signal Process. 22(2): 324-336 (2012) - [j16]Alejandro Rojas, René Cumplido, Jesús Ariel Carrasco-Ochoa
Hardware-software platform for computing irreducible testors. Expert Syst. Appl. 39(2): 2203-2210 (2012) - [j15]Fernando Martin del Campo, Alicia Morales-Reyes
A multi-cycle fixed point square root module for FPGAs. IEICE Electron. Express 9(11): 971-977 (2012) - [c29]Jürgen Becker, Jinian Bian, Christophe Bobda, René Cumplido, Michael Hübner:
RAW Introduction. IPDPS Workshops 2012: 208-212 - [c28]Ignacio Algredo-Badillo
Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm. ISVLSI 2012: 63-68 - 2011
- [j14]Jose Juan Garcia-Hernandez, Claudia Feregrino Uribe, René Cumplido, Carolina Reta
On the Implementation of a Hardware Architecture for an Audio Data Hiding System. J. Signal Process. Syst. 64(3): 457-468 (2011) - [c27]Ignacio Algredo-Badillo
Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 Algorithms. DSD 2011: 543-549 - [c26]Jürgen Becker, Pascal Benoit, René Cumplido:
RAW Introduction. IPDPS Workshops 2011: 125-127 - [c25]Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido, Juan M. Campos:
On a Hybrid and General Control Scheme for Algorithms Represented as a Polytope. IPDPS Workshops 2011: 330-333 - [c24]René Cumplido, Claudia Feregrino Uribe, Jose Juan Garcia-Hernandez:
Invited paper: Implementing digital data hiding algorithms in reconfigurable hardware - Experiences on teaching and research. ReCoSoC 2011: 1-6 - [e4]Peter M. Athanas, Jürgen Becker, René Cumplido:
2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-1734-5 [contents] - 2010
- [j13]Ignacio Algredo-Badillo
Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard. Comput. Electr. Eng. 36(3): 565-577 (2010) - [j12]Roberto Perez-Andrade, René Cumplido, Claudia Feregrino Uribe, Fernando Martin del Campo:
A versatile hardware architecture for a constant false alarm rate processor based on a linear insertion sorter. Digit. Signal Process. 20(6): 1733-1747 (2010) - [j11]Santos López-Estrada, René Cumplido:
Hardware architecture for adaptive filtering based on energy-CFAR processor for radar target detection. IEICE Electron. Express 7(9): 628-633 (2010) - [j10]Jose Juan Garcia-Hernandez, Claudia Feregrino Uribe, René Cumplido, Ramón Parra-Michel:
Improving the security of Fallahpour's audio watermarking scheme. IEICE Electron. Express 7(14): 995-1001 (2010) - [j9]Miguel Morales-Sandoval
A Single Formula and its Implementation in FPGA for Elliptic Curve Point Addition Using Affine Representation. J. Circuits Syst. Comput. 19(2): 425-433 (2010) - [c23]Tomás Balderas-Contreras, Gustavo Rodríguez Gómez
A UML 2.0 Profile to Model Block Cipher Algorithms. ECMFA 2010: 20-31 - [c22]Lázaro Bustio-Martínez
On the Design of a Hardware-Software Architecture for Acceleration of SVM's Training Phase. MCPR 2010: 281-290 - [c21]Alejandro Mesa, Claudia Feregrino Uribe, René Cumplido, José Hernández Palancar:
A Highly Parallel Algorithm for Frequent Itemset Mining. MCPR 2010: 291-300 - [e3]Viktor K. Prasanna, Jürgen Becker, René Cumplido:
ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 13-15 December 2010, Proceedings. IEEE Computer Society 2010 [contents] - [i1]René Cumplido, Juan M. Campos, Claudia Feregrino Uribe, Jose Roberto Perez-Andrade:
Towards a reconfigurable hardware architecture for implementing a LDPC module suitable for software radio systems. Dynamically Reconfigurable Architectures 2010
2000 – 2009
- 2009
- [j8]Miguel Morales-Sandoval
An area/performance trade-off analysis of a GF(2m) multiplier architecture for elliptic curve cryptography. Comput. Electr. Eng. 35(1): 54-58 (2009) - [j7]Jose Juan Garcia-Hernandez, Carolina Reta
Efficient implementation of the RDM-QIM algorithm in an FPGA. IEICE Electron. Express 6(14): 1064-1070 (2009) - [j6]Fernando Martin del Campo, René Cumplido, Roberto Perez-Andrade, Aldo G. Orozco-Lugo:
A System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation. Int. J. Reconfigurable Comput. 2009: 912301:1-912301:10 (2009) - [j5]Roberto Perez-Andrade, René Cumplido, Claudia Feregrino Uribe, Fernando Martin del Campo:
A versatile linear insertion sorter based on an FIFO scheme. Microelectron. J. 40(12): 1705-1713 (2009) - [c20]Pedro Aaron Hernandez-Avalos, Claudia Feregrino Uribe, Roger Luis Velázquez, René Cumplido-Parra:
Watermarking Based on Iterated Function Systems. ENC 2009: 339-344 - [c19]Miguel Morales-Sandoval
A Run Time Reconfigurable Co-processor for Elliptic Curve Scalar Multiplication. ENC 2009: 345-350 - [c18]Santos López-Estrada, René Cumplido:
FPGA-architecture for Knowledge-Based Target Detection in Radar Signal Processing. ERSA 2009: 287-290 - [e2]Viktor K. Prasanna, Lionel Torres, René Cumplido:
ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings. IEEE Computer Society 2009, ISBN 978-0-7695-3917-1 [contents] - 2008
- [j4]Tomás Balderas-Contreras, René Cumplido, Claudia Feregrino Uribe:
On the design and implementation of a RISC processor extension for the KASUMI encryption algorithm. Comput. Electr. Eng. 34(6): 531-546 (2008) - [j3]Ignacio Algredo-Badillo
Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description. IEICE Trans. Inf. Syst. 91-D(10): 2519-2523 (2008) - [c17]Edgar Gomez-Hernández, Claudia Feregrino Uribe, René Cumplido:
FPGA Hardware Architecture of the Steganographic ConText Technique. CONIELECOMP 2008: 123-128 - [c16]Roberto Perez-Andrade, René Cumplido, Claudia Feregrino Uribe, Fernando Martin del Campo:
A versatile hardware architecture for a CFAR detector based on a linear insertion sorter. FPL 2008: 467-470 - [c15]Roberto Perez-Andrade, René Cumplido, Fernando Martin del Campo, Claudia Feregrino Uribe:
A Versatile Linear Insertion Sorter Based on a FIFO Scheme. ISVLSI 2008: 357-362 - [c14]Fernando Martin del Campo, René Cumplido, Roberto Perez-Andrade, Aldo G. Orozco-Lugo:
Hybrid Architecture for Data-Dependent Superimposed Training in Digital Receivers. ReConFig 2008: 355-360 - [c13]Jose Juan Garcia-Hernandez, Claudia Feregrino Uribe, René Cumplido:
FPGA Implementation of a Modulated Complex Lapped Transform for Watermarking Systems. ReConFig 2008: 367-372 - [c12]Ignacio Algredo-Badillo
FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks. ReConFig 2008: 421-426 - [c11]Zobeida Jezabel Guzman-Zavaleta
A Reversible Data Hiding Algorithm for Radiological Medical Images and Its Hardware Implementation. ReConFig 2008: 444-449 - 2007
- [c10]Alejandro Rojas, René Cumplido, Jesús Ariel Carrasco-Ochoa, Claudia Feregrino Uribe, José Francisco Martínez Trinidad
FPGA-Based Architecture for Computing Testors. IDEAL 2007: 188-197 - 2006
- [j2]Virgilio Zúñiga Grajeda, Claudia Feregrino Uribe, René Cumplido-Parra:
Parallel Hardware/Software Architecture for the BWT and LZ77 Lossless Data Compression Algorithms. Computación y Sistemas 10(2) (2006) - [c9]René Cumplido, Jesús Ariel Carrasco-Ochoa, Claudia Feregrino:
On the Design and Implementation of a High Performance Configurable Architecture for Testor Identification. CIARP 2006: 665-673 - [c8]Ignacio Algredo-Badillo
Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture. ICCSA (3) 2006: 456-465 - [c7]Santos López-Estrada, René Cumplido:
Decision Tree Based FPGA-Architecture for Texture Sea State Classification. ReConFig 2006: 191-197 - [e1]René Cumplido-Parra, César Torres-Huitzil, Andrés D. García:
2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006, San Luis Potosi, Mexico, September 20-22, 2006. IEEE Computer Society 2006, ISBN 1-4244-0690-0 [contents] - 2005
- [j1]René Cumplido, Simon R. Jones, Roger Goodall
A high-performance processor for embedded real-time control. IEEE Trans. Control. Syst. Technol. 13(3): 485-492 (2005) - [c6]Tomás Balderas-Contreras, René Cumplido:
High performance encryption cores for 3G networks. DAC 2005: 240-243 - [c5]Santos López-Estrada, René Cumplido-Parra:
Fusion center with neural network for target detection in background clutter. ENC 2005: 189-197 - [c4]Joaquín García, René Cumplido-Parra:
On the design of an FPGA-based OFDM modulator for IEEE 802.16-2004. ReConFig 2005 - [c3]José Francisco Martínez Trinidad, René Cumplido-Parra, Claudia Feregrino Uribe:
An FPGA-based parallel sorting architecture for the Burrows Wheeler transform. ReConFig 2005 - 2004
- [c2]Santos López-Estrada, René Cumplido-Parra, César Torres-Huitzil:
A Hybrid Approach for Target Detection Using CFAR Algorithm and Image Processing. ENC 2004: 108-115 - [c1]César Torres-Huitzil, René Cumplido-Parra, Santos López-Estrada:
Design and Implementation of a CFAR Processor for Target Detection. FPL 2004: 943-947 - 2001
- [b1]René Cumplido-Parra:
On the design and implementation of a control system processor. Loughborough University, UK, 2001
Coauthor Index
Lázaro Bustio-Martínez
aka: Lázaro Bustio
aka: Lázaro Bustio
José Juan García-Hernández
aka: Jose Juan Garcia-Hernandez
aka: Jose Juan Garcia-Hernandez
Roberto Perez-Andrade
aka: Jose Roberto Perez-Andrade
aka: Jose Roberto Perez-Andrade
Claudia Feregrino Uribe
aka: Claudia Feregrino
aka: Claudia Feregrino
[j52] [j51] [j48] [j47] [j46] [j45] [j44] [j43] [j42] [j41] [j40] [c47] [e8] [j39] [e7] [c46] [c45] [c44] [e6] [j34] [j33] [j32] [c41] [j30] [j28] [j26] [j25] [c36] [j24] [j23] [j20] [c33] [c31] [c30] [j17] [j16] [j15] [c28] [j14] [c27] [c24] [j13] [j12] [j10] [j9] [c22] [c21] [i1] [j8] [j7] [j5] [c20] [c19] [j4] [j3] [c17] [c16] [c15] [c13] [c12] [c11] [c10] [j2] [c9] [c8] [c3]
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