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On the Implementation of a Hardware Architecture for an Audio Data Hiding System

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Abstract

Data hiding systems have emerged as a solution against the piracy problem, particularly those based on quantization have been widely used for its simplicity and high performance. Several data hiding applications, such as broadcasting monitoring and live performance watermarking, require a real-time multi-channel behavior. While Digital Signal Processors (DSP) have been used for implementing these schemes achieving real-time performance for audio signal processing, custom hardware architectures offer the possibility of fully exploiting the inherent parallelism of this type of algorithms for more demanding applications. This paper presents an efficient hardware implementation of a Rational Dither Modulation (RDM) algorithm-based data hiding system in the Modulated Complex Lapped Transform (MCLT) domain. In general terms, the proposed hardware architecture is conformed by an MCLT processor, an Inverse MCLT processor, a Coordinate Rotation Digital Computer (CORDIC) and an RDM-QIM processor. Results of implementing the proposed hardware architecture on a Field Programmable Gate Array (FPGA) are presented and discussed.

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Notes

  1. These implementations were previously reported by the authors in [33]

  2. The same workstation is used for software implementatios along this work.

  3. This implementation was previously reported by the authors in [36]

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Acknowledgement

The authors would like to thank CONACyT for financial support.

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Correspondence to Claudia Feregrino-Uribe.

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Garcia-Hernandez, J.J., Feregrino-Uribe, C., Cumplido, R. et al. On the Implementation of a Hardware Architecture for an Audio Data Hiding System. J Sign Process Syst 64, 457–468 (2011). https://doi.org/10.1007/s11265-010-0503-8

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