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Journal of Electronic Testing, Volume 23
Volume 23, Number 1, February 2007
- Vishwani D. Agrawal:
Editorial. 5 - Bruce C. Kim:
Test Technology Newsletter. 9-10 - Chunsheng Liu:
Improve the Quality of Per-Test Fault Diagnosis Using Output Information. 11-24 - Ugur Çilingiroglu
:
Magnetic In-circuit Testing of Multiple Power and Ground Pins for Open Faults. 25-34 - Grzegorz Mrugalski, Janusz Rajski, Chen Wang, Artur Pogiel, Jerzy Tyszer:
Isolation of Failing Scan Cells through Convolutional Test Response Compaction. 35-45 - Luca Sterpone
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs. 47-54 - Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian:
Minimal March Tests for Detection of Dynamic Faults in Random Access Memories. 55-74 - Wang-Dauh Tseng:
Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing. 75-84 - Dana Brown, John Ferrario, Randy Wolf, Jing Li, Jayendra Bhagat, Mustapha Slamani:
RF Testing on a Mixed Signal Tester. 85-94 - Shalabh Goyal, Abhijit Chatterjee, Michael Purtell:
A Low-Cost Test Methodology for Dynamic Specification Testing of High-Speed Data Converters. 95-106
Volume 23, Numbers 2-3, June 2007
- Vishwani D. Agrawal:
Editorial. 111 - Bruce C. Kim:
Test Technology Newsletter April 2007. 113-114 - Mohammad Tehranipoor:
Guest Editorial. 115-116 - Tad Hogg, Greg Snider:
Defect-tolerant Logic with Nanoscale Crossbar Circuits. 117-129 - Jason G. Brown, R. D. (Shawn) Blanton:
A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology. 131-144 - Zhanglei Wang, Krishnendu Chakrabarty
Built-in Self-test and Defect Tolerance in Molecular Electronics-based Nanofabrics. 145-161 - Jing Huang, Mariam Momenzadeh, Fabrizio Lombardi:
On the Tolerance to Manufacturing Defects in Molecular QCA Tiles for Processing-by-wire. 163-174 - Jia Di, Parag K. Lala:
Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems. 175-192 - Sanjukta Bhanja, Marco Ottavi
QCA Circuits for Robust Coplanar Crossing. 193-210 - Mo Liu, Craig S. Lent:
Reliability and Defect Tolerance in Metallic Quantum-dot Cellular Automata. 211-218 - Fei Su, William L. Hwang, Arindam Mukherjee, Krishnendu Chakrabarty
Testing and Diagnosis of Realistic Defects in Digital Microfluidic Biochips. 219-233 - Wenjing Rao, Alex Orailoglu, Ramesh Karri
Towards Nanoelectronics Processor Architectures. 235-254 - Kundan Nepal, R. Iris Bahar
Designing Nanoscale Logic Circuits Based on Markov Random Fields. 255-266
Volume 23, Number 4, August 2007
- Erik Schüler, Marcelo Ienczczak Erigson, Luigi Carro
Functionally Fault-tolerant DSP Microprocessor using Sigma-delta Modulated Signals. 275-292 - J. M. Gilbert, Ian M. Bell:
The Effectiveness of Test in Controlling Quality Costs: A Conformability Analysis Based Approach. 293-307 - John W. Sheppard
A Formal Analysis of Fault Diagnosis with D-matrices. 309-322 - M. A. El-Gamal, M. D. A. Mohamed:
Ensembles of Neural Networks for Fault Diagnosis in Analog Circuits. 323-339 - Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. 341-355 - Sunghoon Chun, YongJoon Kim, Sungho Kang:
MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs. 357-362 - Mohammad Gh. Mohammad
Techniques for Disturb Fault Collapsing. 363-368
Volume 23, Number 5, October 2007
- Vishwani D. Agrawal:
Editorial. 369 - Bruce C. Kim:
Test Technology Newsletter - October 2007. 371-372 - Franco Fummi, Graziano Pravadelli
Too Few or Too Many Properties? Measure it by ATPG! 373-388 - Paolo Bernardi
A System-layer Infrastructure for SoC Diagnosis. 389-404 - Fatih Kocan, Daniel G. Saab:
Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware. 405-420 - Walid Ibrahim
A Novel EDA Tool for VLSI Test Vectors Management. 421-434 - Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits. 435-444 - Ilia Polian, Hideo Fujiwara:
Functional Constraints vs. Test Compression in Scan-Based Delay Testing. 445-455 - David Hély
Securing Scan Control in Crypto Chips. 457-464
Volume 23, Number 6, December 2007
- Vishwani D. Agrawal:
Editorial. 465 - Bruce C. Kim:
Test Technology Newsletter - December 2007. 467-468 - Marcelo Lubaszewski, Andrew Richardson
Guest Editorial. 469 - Ahcène Bounceur, Salvador Mir, Emmanuel Simeu, Luís Rolíndez:
Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing. 471-484 - Uros Kac, Franc Novak:
Oscillation Test Scheme of SC Biquad Filters Based on Internal Reconfiguration. 485-495 - Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell:
Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis. 497-512 - Carsten Wegener, Michael Peter Kennedy
Hard-Fault Detection and Diagnosis During the Application of Model-Based Data Converter Testing. 513-525 - Hao-Chiao Hong
A Fully-Settled Linear Behavior Plus Noise Model for Evaluating the Digital Stimuli of the Design-for-Digital-Testability Sigma-Delta Modulators. 527-538 - Daniela De Venuto
Fast PWM-Based Test for High Resolution SigmaDelta ADCs. 539-548 - Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu, Soon-Jyh Chang:
Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST. 549-558 - Lei Ma, Geert Seuren, Robert Van Rijsinge, Corné Bastiaansen, Leon van der Dussen:
A Design-Based Structural Test Method for a Switched-Resistor DAC. 559-567 - Teuvo Saikkonen, Markku Moilanen:
Component Value Calculations and Characterizations for Measurements in the IEEE 1149.4 Environment. 569-579 - Jari Hannu
Methods of Testing Discrete Semiconductors in the 1149.4 Environment. 581-592 - Mikaël Cimino, Hervé Lapuyade, M. De Matos, Thierry Taris, Yann Deval
A Robust 130 nm-CMOS Built-In Current Sensor Dedicated to RF Applications. 593-603 - Kay Suenaga, Rodrigo Picos
A Module for BiST of CMOS RF Receivers. 605-612 - Marcelo Negreiros
Reducing Test Time Using an Enhanced RF Loopback. 613-623 - Cristiano Lazzari, Ricardo A. L. Reis, Lorena Anghel
A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis. 625-633
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