A Novel EDA Tool for VLSI Test Vectors Management

1. Aickelin U (2002) An indirect genetic algorithm for set covering problems. J Oper Res Soc 53:1118–1126

   Article  MATH  Google Scholar 

2. Balas E, Carrera MC (1996) A dynamic subgradient-based branch-and-bound procedure for set covering. Eur J Oper Res 44:875–890, November

   MATH  MathSciNet  Google Scholar 

3. Beasley JE, Chu PC (1996) A genetic algorithm for the set covering problem. Eur J Oper Res 94:392–404, October

   Article  MATH  Google Scholar 

4. Beiu V, Rückert U, Roy S, Nyathi J (2004) On nanoelectronic architectural challenges and solutions. Proc IEEE Conf Nanotech, IEEE-NANO’04, Munich, Germany, pp 628–631, Aug.

5. Bourianoff GI (2003) The future of nanocomputing. IEEE Comput 36:44–53, August

   Google Scholar 

6. Bryant RE, Cheng KT, Kahng AB, Keutzer K, Maly W, Newton R, Pillegi L, Rabaey JM, Sangiovanni-Vincentelli A (2001) Limitations and challenges for computer-aided design technology for CMOS VLSI. Proc IEEE 89:341–365, March

   Article  Google Scholar 

7. Cadence Functional Verification Kit for ARM, available at, http://www.cadence.com/datasheets/arm_func _ver_kit.pdf

8. Cheng W-T (2000) Current status and future trend on CAD tools for VLSI testing. Proc 9th Asian Test Symp, ATS’00, Taipei, Taiwan pp 10–11, December

9. Corno F, Prinetto P, Rebaudengo M, Sonza Reorda M, Veiluva E (1995) A portable ATPG tool for parallel and distributed systems. IEEE VLSI Test Symp, Princeton, USA, pp 29–34, April

10. Corno F, Rebaudengo M, Sonza Reorda M, Violante M (1999) Optimal vector selection for low power BIST. Proc IEEE Int Symp on Defect & Fault Tolerance in VLSI Sys., DFT’99, Albuquerque, New Mexico, USA, pp 219–226, November

11. Davis JA, Venkatesan R, Kaloyeros A, Beylansky M, Souri SJ, Banerjee K, Saraswat KC, Rahman A, Reif R, Meindl JD (2001) Interconnect Limits on Gigascale Integration (GSI) in the 21st Century. Proc. IEEE 89:305–324, March

    Article  Google Scholar 

12. De Bontridder KMJ, Halldorsson BV, Halldorsson MM, Hurkens CAJ, Lenstra JK, Ravi R, Stougie L (2003) Approximation algorithms for the test cover problem. Math Program 98:477–491

    Article  MATH  MathSciNet  Google Scholar 

13. De Bontridder KMJ, Lageweg BJ, Lenstra JK, Orlin JB, Stougie L (2002) Branch-and-bound algorithms for the test cover problem. Proc of the 10th Eur Symp on Alg (ESA’02) vol. 2461, Springer, Heidelberg, pp 223–233

14. Edbom S, Larsson E (2004) An integrated technique for test vector selection and test scheduling under test time constraint. Proc 13th Asian Test Symp 254–257, November

15. Forshaw M, Stadler R, Crawley D, Nicoliæ K (2004) A short review of nanoelectronic architectures. Nanotechnology 15:S220–S223, April

    Article  Google Scholar 

16. Frank DJ, Dennard RH, Nowak E, Solomon PM, Taur Y, Wong H-SP (2001) Device scaling limits of Si MOSFETs and their application dependencies. Proc IEEE 89(3):259–288, March

    Article  Google Scholar 

17. GAlib, “A C++ Library of Genetic Algorithm Components”, version 2.4.6. Available at http://lancet.mit.edu/ga/

18. Garey MR, Johnson DS (1979) Computers and intractability: A guide to the theory of NP-completeness, Freeman, San Francisco

    MATH  Google Scholar 

19. Grosman T, Wool A (1997) Computational experience with approximation algorithms for the set covering problem. Eur J Oper Res 101:81–92, August

    Article  Google Scholar 

20. Harlow JE III (2003) Toward design technology in 2020: Trends, issues, and challenges. Proc Intl Symp VLSI (ISVLSI’03), Tampa, FL, USA, pp 3–4, February

21. International Technology Roadmap for Semiconductors (ITRS), 2005 Edition and 2006 Update, Intl. SEMATECH, Austin, TX, USA, Available at http://public.itrs.net/

22. Krishnamurthy N, Abadir MS, Martin AK, Abraham JA (2001) Design and development paradigm for industrial formal verification CAD tools. IEEE Des Test Comput 18:26–35, August

    Article  Google Scholar 

23. Lajolo M, Rebaudengo M, Reorda MS, Violante M, Lavagno L (2000) Behavioral-level test vector generation for system-on-chip sesigns. Proc IEEE Int. High-Level Design Validation and Test Workshop, Berkeley, CA, USA, pp 21–26, November

24. Li J, Kwan RSK (2004) A meta-heuristic with orthogonal experiment for the set covering problem. J Math Model Algorithms 3:263–283

    Article  MATH  MathSciNet  Google Scholar 

25. Lp_solve, “A Free Linear (integer) Programming Solver, version 5.1.1.3. available at http://lpsolve. sourceforge.net/5.1/

26. Mead C, Conway L (1980) Introduction to VLSI systems. Addision-Wesley

27. Meindl JD, Chen Q, Davis JA (2001) Limits on silicon nanoelectronics for terascale integration. Science 293(553):2044–2049, September

    Article  Google Scholar 

28. Moret B, Shapiro H (1985) On minimizing a set of tests. Siam J Sci Statist Comput 6:983–1003

    Article  Google Scholar 

29. Ohlsson M, Peterson C, Söberderg B (2001) An efficient mean field approach to the set covering problem. Eur J Oper Res 133:583–599, September

    Article  MATH  Google Scholar 

30. Roychowdhury VP, Janes DB, Bandyopadhyay S (1997) Nanoelectronic architectures for Boolean logic. Proc IEEE 85:574–588, April

    Article  Google Scholar 

31. Sakurai T (2000) Design challenges for 0.1 μm and beyond. Proc. Asia & South Pacific Design Autom Conf (ASP-DAC’00), Tokyo, Japan, pp 553–558, January

32. Sen S (1993) Minimal cost set covering using probabilistic methods. Proc ACM Symp on Applied Comp: States of the Art and Practice, pp 157–164

33. Solar M, Parada V, Urrutia R (2002) A parallel genetic algorithm to solve the set-covering problem. Comput Oper Res 29(9):1221–1235, August

    Article  MATH  MathSciNet  Google Scholar 

34. Synopsis Discovery Verification Platform, available at http://www.synopsys.com/products/solutions/ discovery_platform.html

Download references